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advisory november 1998 t7234, t7237, and t7256 compliance with the new etsi psd requirement (refer to the t7234, t7237, and t7256 isdn transceiver data sheets.) telecommunication standard the european telecommunications standards institute (etsi) has identified a change in the requirement of the power spectral density (psd) for basic rate interface isdn. section a.12.4, power spectral density, of etsi ts080 states the following: n the upper boundary of the power spectral density of the transmitted signal shall be as shown in figure 1, below. n measurements to verify compliance with this requirement are to use a noise power bandwidth of 1.0 khz. n systems deployed before january 1, 2000 do not have to meet this psd requirement but shall meet the psd requirements as defined in etr 080 edition 2. it is, however, expected that these systems will also meet the psd requirements of ts080 edition 3. some narrowband violations could occur and should be tolerated. 5-7388f figure 1. upper boundary of power spectral density from nt1 and lt the existing scnt1 family (t7234a, T7237A, and t7256a) of u-interface transceivers fully comply with this standard. conformance to the above requirement has been fully verified, and test reports are available upon request. C130 C120 C110 C100 C90 C80 C70 C60 C50 C40 C30 0.010 1.000 0.100 10.000 f (mhz) C140 100.000 psd (dbm/hz) C20 0.001 0.050 0.315 1.000 5.000 30.000
lucent technologies inc. reserves the right to make changes to the product(s) or information contained herein without notice. n o liability is assumed as a result of their use or application. no rights under any patent accompany the sale of any such product(s) or information. copyright ? 1998 lucent technologies inc. all rights reserved printed in u.s.a. november 1998 ay99-004isdn (must accompany ds97-410isdn, ds97-411isdn, ds97-412isdn, and ay98-025isdn) for additional information, contact your microelectronics group account manager or the following: internet: http://www.lucent.com/micro e-mail: docmaster@micro.lucent.com n. america: microelectronics group, lucent technologies inc., 555 union boulevard, room 30l-15p-ba, allentown, pa 18103 1-800-372-2447 , fax 610-712-4106 (in canada: 1-800-553-2448 , fax 610-712-4106) asia pacific: microelectronics group, lucent technologies singapore pte. ltd., 77 science park drive, #03-18 cintech iii, singap ore 118256 tel. (65) 778 8833 , fax (65) 777 7495 china: microelectronics group, lucent technologies (china) co., ltd., a-f2, 23/f, zao fong universe building, 1800 zhong shan xi road, shanghai 200233 p. r. china tel. (86) 21 6440 0468 , ext. 316 , fax (86) 21 6440 0652 japan: microelectronics group, lucent technologies japan ltd., 7-18, higashi-gotanda 2-chome, shinagawa-ku, tokyo 141, japan tel. (81) 3 5421 1600 , fax (81) 3 5421 1700 europe: data requests: microelectronics group dataline: tel. (44) 1189 324 299 , fax (44) 1189 328 148 technical inquiries: germany: (49) 89 95086 0 (munich), united kingdom: (44) 1344 865 900 (ascot), france: (33) 1 40 83 68 00 (paris), sweden: (46) 8 594 607 00 (stockholm), finland: (358) 9 4354 2800 (helsinki), italy: (39) 02 6608131 (milan), spain: (34) 1 807 1441 (madrid)
advisory july 1998 t7234, t7237, and t7256 data sheet advisory (refer to the t7234, t7237, and t7256 isdn transceiver data sheets.) the technology and telecommunications standard sections below denote the differences between the t7234, t7237, and t7256 and the t7234a, T7237A, and t7256a. technology n the t-7234- - -ml, t-7237- - -ml, and t-7256- - -ml2 are 0.9 m cmos technology devices. n the t-7234a- -ml, t-7237a- -ml, and t-7256a- -ml are 0.6 m cmos technology devices. telecommunication standard in 1996, the european telecommunications standards institute (etsi) added a microinterruption immunity requirement to etr 080 (sections 5.4.5 and 6.2.5). section 5.4.5 in etsi etr 080 states the following: n a microinterruption is a temporary line interruption due to external mechanical activity on the copper wires constituting the transmission path. n the effect of a microinterruption on the transmission system can be a failure of the digital transmission link. n the objective of this requirement is that the presence of a microinterruption of specified maximum length shall not deactivate the system, and the system shall activate if it has deactivated due to longer interruption. section 6.2.5 in etsi etr 080 states that: n a system shall tolerate a microinterruption up to t = 5 ms, when simulated with a repetition interval of t = 5 ms. the scnt1 family of u-interface transceivers was upgraded to fully comply with this standard. the devices have been given an a suffix (t7234a, T7237A, and t7256a). a proposal was added to the living list (which is intended to collect issues and observations for a possible future update of etsi etr 080) to change the value of the microinterruption from 5 ms to 10 ms. the current scnt1 family of u-interface transceivers (t7234a/T7237A/t7256a) from lucent technologies microelectron- ics group meets and exceeds this new requirement. the above change to the scnt1 family of transceivers has been fully verified, and test reports are available upon request.
lucent technologies inc. reserves the right to make changes to the product(s) or information contained herein without notice. n o liability is assumed as a result of their use or application. no rights under any patent accompany the sale of any such product(s) or information. copyright ? 1998 lucent technologies inc. all rights reserved printed in u.s.a. july 1998 ay98-025isdn (replaces ay98-020isdn) (must accompany ds97-410isdn, ds97-411isdn, and ds97-412isdn) for additional information, contact your microelectronics group account manager or the following: internet: http://www.lucent.com/micro e-mail: docmaster@micro.lucent.com n. america: microelectronics group, lucent technologies inc., 555 union boulevard, room 30l-15p-ba, allentown, pa 18103 1-800-372-2447 , fax 610-712-4106 (in canada: 1-800-553-2448 , fax 610-712-4106) asia pacific: microelectronics group, lucent technologies singapore pte. ltd., 77 science park drive, #03-18 cintech iii, singap ore 118256 tel. (65) 778 8833 , fax (65) 777 7495 china: microelectronics group, lucent technologies (china) co., ltd., a-f2, 23/f, zao fong universe building, 1800 zhong shan xi road, shanghai 200233 p. r. china tel. (86) 21 6440 0468 , ext. 316 , fax (86) 21 6440 0652 japan: microelectronics group, lucent technologies japan ltd., 7-18, higashi-gotanda 2-chome, shinagawa-ku, tokyo 141, japan tel. (81) 3 5421 1600 , fax (81) 3 5421 1700 europe: data requests: microelectronics group dataline: tel. (44) 1189 324 299 , fax (44) 1189 328 148 technical inquiries: germany: (49) 89 95086 0 (munich), united kingdom: (44) 1344 865 900 (bracknell), france: (33) 1 48 83 68 00 (paris), sweden: (46) 8 600 7070 (stockholm), finland: (358) 9 4354 2800 (helsinki), italy: (39) 2 6601 1800 (milan), spain: (34) 1 807 1441 (madrid) advisory july 1998 data sheet advisory t7234, t7237, and t7256 application circuit please change the value of capacitor c15 from 0.1 f to 1.0 f in figure 11 of the t7234 data sheet, figure 17 of the t7237 data sheet, and figure 20 of the t7256 data sheet. the following schematic shows the correct value (1.0 f) for c15. 5-7034(c) figure 1. mlt circuit showing new placement of zener diode (z d ) and capacitor (c a ) in the iloss mode (refer to ansi t1.601 1992, section 6.5.2), the nt generates a scrambled, framed, 2b1q sig- nal such as sn1 and sn2. when the iloss mode is applied to circuits with the lh1465, it was observed that for some short loop lengths, the nt, once in the iloss mode, would not respond to further maintenance pulses until the iloss timer expired. it was discovered that there is some portion of the transmitted 2b1q signal from the nt that passes through the lh1465 to the optoisolator. this causes the optoisolator to report incorrect dial pulses at its output, and thus prevent the nt from properly exiting the iloss mode. to correct this situation, the dropout voltage (voltage at the tip/ring needed to turn on the optoisolator) of the optoisolator driver on the lh1465 is raised using the 3.6 v zener diode z d (for example, motorola * mmsz4685t1). capacitor c a is a 1.0 f 10% tantalum chip capacitor, with a voltage rating of at least 16 v. c a is added to provide a level of filtering for the transition points (turn-on or turn-off) of the optoisolator input voltage, which increases the robustness of the circuit. * motorola is a registered trademark of motorola inc. r14 1.1 k w 2 w pr+ t r pr u3 lh1465ab 1 2 3 4 tc rs pd com 8 7 6 5 r12 137 w c15 1.0 ? r10 10 k w r8 17.8 k w +5 v r9 2.2 m w 5 6 8 2 3 u2 hcpl-0701 7 c a 1.0 ? mlt circuit for north american applications only r15 1.1 k w 2 w r11 137 w (place this capacitor as close as possible to the lh1465) z d ring tip scnt1 optoin pin
data sheet january 1998 t7256 single-chip nt1 (scnt1) transceiver features n u- to s/t-interface conversion for isdn basic rate (2b+d) systems ?integrated u- and s/t-interfaces ?operates in stand-alone mode to provide u- and s/t-interface activation, control, and mainte- nance functions ?serial microprocessor and time-division multi- plexed (tdm) bus interfaces for enhanced nt1 operation and voice/data ports ?automatic embedded operations channel (eoc) processing for ansi t1.601 systems ?low power consumption supporting line-pow- ered nt1 (see table 45 on page 102, question and answers section, #53 for detailed power consumption information.) ?idle-mode support (35 mw typical) ?board-level testability support n u-interface ?conforms to ansi t1.601 standard and etsi etr 080 technical report ?2b1q four-level line code ?automatic ansi maintenance functions (quiet mode and insertion loss mode) n s/t-interface ?conforms to ansi t1.605 standard, itu-t i.430 recommendation, and etsi ets 300 012 for nt operation ?supports point-to-point and point-to-multipoint (passive bus) arrangements ?supports s- and q-channel multiframing opera- tions (an external microprocessor is required for s- and q-channel multiframing support) n serial microprocessor and tdm bus interfaces ?supports inexpensive serial microprocessor ?supports direct codec connection and voice/ data ports ?allows access to 2b+d data on tdm bus n other ?single +5 v ( 5%) supply ??0 c to +85 c ?44-pin plcc description the lucent technologies microelectronics group t7256 single-chip nt1 (scnt1) transceiver inte- grated circuit provides data (2b+d) and control infor- mation conversion between 2-wire (u-interface) and 4-wire (s/t-interface) digital subscriber loops on the integrated services digital network (isdn). the t7256 conforms to the ansi t1.601 standard and etsi etr 080 technical report for the u-interface and the itu-t i.430 recommendation, ansi t1.605 standard, and etsi ets 300 012 for the s/t-inter- face. the t7256 also supports digital pair gain and terminal adapter applications. the single +5 v cmos device is packaged in a 44-pin plastic leaded chip carrier (plcc).
data sheet t7256 single-chip nt1 (scnt1) transceiver january 1998 2 lucent technologies inc. table of contents contents page features .................................................................................................................................................................... 1 description ................................................................................................................................................................ 1 pin information .......................................................................................................................................................... 5 application overview ............................................................................................................................................... 10 functional overview ................................................................................................................................................ 11 u-interface frame structure .................................................................................................................................... 12 bit assignments....................................................................................................................................................... 13 s/t-interface frame structure.................................................................................................................................. 14 u-interface description............................................................................................................................................ 17 s/t-interface description ......................................................................................................................................... 18 microprocessor interface description ...................................................................................................................... 18 registers.......................................................................................................................................................... 18 timing .............................................................................................................................................................. 39 time-division multiplexed (tdm) bus description .................................................................................................. 41 clock and data format .................................................................................................................................... 41 frame strobe ................................................................................................................................................... 41 data flow matrix description................................................................................................................................... 43 b1-, b2-, d-channel routing ........................................................................................................................... 43 loopbacks ............................................................................................................................................................... 44 modes of operation ................................................................................................................................................. 45 stled description .................................................................................................................................................. 46 eoc state machine description................................................................................................................................ 48 ansi maintenance control description ................................................................................................................... 48 s/t-interface multiframing controller description .................................................................................................... 49 board-level testing ......................................................................................................................................... 50 stimulus/response testing.............................................................................................................................. 50 application briefs..................................................................................................................................................... 52 t7256 reference circuit .................................................................................................................................. 52 using the t7256 in a combination te/ta environment (nt1/ta) ................................................................... 59 t7256 con?uration ........................................................................................................................................ 59 d-channel priority ........................................................................................................................................... 60 interfacing the t7256 to the motorola 68302 ................................................................................................... 62 available tools for evaluation of the t7256 ..................................................................................................... 69 absolute maximum ratings..................................................................................................................................... 73 handling precautions .............................................................................................................................................. 73 recommended operating conditions ..................................................................................................................... 73 electrical characteristics ......................................................................................................................................... 74 power consumption......................................................................................................................................... 74 pin electrical characteristics ........................................................................................................................... 74 s/t-interface receiver common-mode rejection............................................................................................ 75 crystal characteristics..................................................................................................................................... 75 timing characteristics ............................................................................................................................................. 76 switching test input/output waveform ............................................................................................................ 78 propagation delay ........................................................................................................................................... 78 outline diagram....................................................................................................................................................... 79 44-pin plcc.................................................................................................................................................... 79 ordering information................................................................................................................................................ 79 questions and answers........................................................................................................................................... 80 introduction ...................................................................................................................................................... 80 u-interface ....................................................................................................................................................... 80 s/t-interface..................................................................................................................................................... 88 miscellaneous .................................................................................................................................................. 99 glossary ................................................................................................................................................................ 105 standards documentation ..................................................................................................................................... 109
data sheet january 1998 t7256 single-chip nt1 (scnt1) transceiver lucent technologies inc. 3 table of contents (continued) figures page figure 1. block diagram ......................................................................................................................................... 5 figure 2. pin diagram............................................................................................................................................. 5 figure 3. applications of t7256............................................................................................................................ 10 figure 4. u-interface frame and superframe ...................................................................................................... 12 figure 5. u-interface superframe bit groups....................................................................................................... 13 figure 6. frame structures of nt and te frames ............................................................................................... 14 figure 7. details of nt and te frames................................................................................................................ 15 figure 8. multiframing? subchannels and q subchannels .............................................................................. 16 figure 9. u-interface quat example..................................................................................................................... 17 figure 10. s/t-interface asi example.................................................................................................................. 18 figure 11. functional register map (addresses and bit assignments) ............................................................... 19 figure 12. nec and motorola microprocessor port connections......................................................................... 39 figure 13. intel microprocessor port connections ............................................................................................... 39 figure 14. synchronous microprocessor port interface format........................................................................... 40 figure 15. tdm bus time-slot format................................................................................................................. 42 figure 16. b1-, b2-, d-channel routing............................................................................................................... 43 figure 17. location of the loopback configurations (reference itu-t i.430 appendix i)................................... 44 figure 18. stled control flow diagram ............................................................................................................. 47 figure 19. external stimulus/response configuration......................................................................................... 51 figure 20. t7256 stand-alone reference circuit-a ............................................................................................. 54 figure 21. t7256 stand-alone reference circuit-b ............................................................................................. 55 figure 22. t7256 nt1/ta application block diagram.......................................................................................... 59 figure 23. mc68302 to t7256 interface diagram ................................................................................................ 62 figure 24. scnt1-rdb epld schematic............................................................................................................ 64 figure 25. scnt1-rdb epld adhl design files .............................................................................................. 65 figure 26. scnt1-rdb epld timing (8-bit) ....................................................................................................... 66 figure 27. scnt1-rdb epld timing (7-bit) ....................................................................................................... 67 figure 28. tdm bus timing.................................................................................................................................. 76 figure 29. timing diagram referenced to syn8k............................................................................................... 77 figure 30. reset timing diagram ...................................................................................................................... 77 figure 31. switching test waveform.................................................................................................................... 78 figure 32. transceiver impedance limits ............................................................................................................ 82 figure 33. receiver bias ...................................................................................................................................... 90 figure 34. t7256 s/t line interface scheme....................................................................................................... 94 figure 35. t7903 s/t line interface scheme....................................................................................................... 94 figure 36. t7250c s/t line interface scheme .................................................................................................... 95 figure 37. t7903 to t7256 direct-connect scheme............................................................................................ 96 figure 38. t7250c to t7256 direct-connect scheme ......................................................................................... 96 figure 39. t7903 to t7256 direct-connect scheme with external s/t-interface ................................................ 97 figure 40. t7250c to t7256 direct-connect scheme with external s/t-interface.............................................. 98
data sheet t7256 single-chip nt1 (scnt1) transceiver january 1998 4 lucent technologies inc. table of contents (continued) tables page table 1. pin descriptions ........................................................................................................................................... 6 table 2. u-interface bit assignment ........................................................................................................................ 13 table 3. line transmission code ............................................................................................................................. 18 table 4. global device control?evice con?uration (address 00h) .................................................................... 20 table 5. global device control?-interface (address 01h) ................................................................................... 22 table 6. global device control?/t-interface (address 02h) ................................................................................. 23 table 7. data flow control? and s/t b channels (address 03h)........................................................................ 25 table 8. data flow control? channels and tdm bus (address 04h).................................................................. 26 table 9. tdm bus timing control (address 05h)..................................................................................................... 27 table 10. control flow state machine control?aintenance/reserved bits (address 06h) ................................. 28 table 11. control flow state machine status (address 07h) .................................................................................. 29 table 12. control flow state machine status?eserved bits (address 08h) ........................................................ 30 table 13. eoc state machine control?ddress (address 09h) .............................................................................. 31 table 14. eoc state machine control?nformation (address 0ah) ......................................................................... 32 table 15. eoc state machine status?ddress (address 0bh) ............................................................................... 32 table 16. eoc state machine status?nformation (address 0ch) .......................................................................... 32 table 17. q-channel bits (address 0dh)................................................................................................................. 33 table 18. s subchannels 1? (address 0eh?2h)............................................................................................... 33 table 19. u-interface interrupt register (address 13h) ........................................................................................... 34 table 20. u-interface interrupt mask register (address 14h).................................................................................. 35 table 21. s/t-interface interrupt register (address 15h)......................................................................................... 36 table 22. s/t-interface interrupt mask register (address 16h) ............................................................................... 36 table 23. maintenance interrupt register (address 17h) ........................................................................................ 37 table 24. maintenance interrupt mask register (address 18h)............................................................................... 37 table 25. global interrupt register (address 19h) .................................................................................................. 38 table 26. stand-alone mode ................................................................................................................................... 45 table 27. microprocessor mode............................................................................................................................... 45 table 28. stled states .......................................................................................................................................... 46 table 29. t7256 reference schematic parts list .................................................................................................... 56 table 30. line-side resistor requirements ............................................................................................................ 58 table 31. motorola mc68302 scc options............................................................................................................. 62 table 32. pcm channel selection ........................................................................................................................... 63 table 33. spec_v2 functions ................................................................................................................................ 69 table 34. spec_v2 interface connector pinouts.................................................................................................... 71 table 35. power consumption ................................................................................................................................. 74 table 36. digital dc characteristics (over operating ranges) ................................................................................ 74 table 37. s/t-interface receiver common-mode rejection .................................................................................... 75 table 38. fundamental mode crystal characteristics ............................................................................................. 75 table 39. internal pll characteristics ..................................................................................................................... 75 table 40. tdm bus timing....................................................................................................................................... 76 table 41. clock timing............................................................................................................................................. 77 table 42. reset timing.......................................................................................................................................... 77 table 43. power dissipation variation .................................................................................................................... 101 table 44. power dissipation of ckout ................................................................................................................. 101 table 45. power consumption ............................................................................................................................... 102
data sheet january 1998 t7256 single-chip nt1 (scnt1) transceiver lucent technologies inc. 5 description (continued) 5-2292 (c) figure 1. block diagram pin information note: pin labels shown in bold (pins 11, 12, and 15) represent chip configuration controls that are sampled on the rising edge of reset (see table 1, pin descriptions). 5-2296 (c) figure 2. pin diagram 2-wire 2b1q u-interface u trans- ceiver crystal osc. 15.360 mhz s/t trans- ceiver 4-wire s/t-interface ? interface eoc state machine multi- framing controller tdm bus interface ansi maintenance decoder tdm bus interface ? interface & registers data flow matrix control flow state machine t7256 6 gnd o v ddo x1 vrcm rpr rnr gnd a tpr tnr v dda v ddd syn8k/lbind/fs gnd a gnd a v dda gnd d stled 54 40 41 42 43 44 1 2 3 19 20 18 28 27 26 25 24 23 22 21 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 v dda sdinp sdinn hp lon gnd a v dda lop hn vrn vrp fte/tdmdi ps2e/tdmdo ps1e/tdmclk gnd d syn8k_ctl /sdi v ddd sdo autoact /sck gnd d ckout iloss optoin highz reset actmode /int x2
data sheet t7256 single-chip nt1 (scnt1) transceiver january 1998 6 lucent technologies inc. pin information (continued) table 1. pin descriptions * i u = input with internal pull-up. pin symbol type* name/function 1, 10, 16 gnd d digital ground. ground leads for digital circuitry. 2 optoin i u optoisolator input. pin accepts cmos logic level maintenance pulse streams. these pulse streams typically are generated by an optoisolator that is monitoring the u loop. pulse patterns on this pin are digitally filtered for 20 ms before being considered valid and are then decoded and interpret- ed using the ansi maintenance state machine requirements. if autoctl = 1 (register gr0, bit 3, default), the internal state machine decodes pulse trains and implements the required maintenance states automatically. if au- toctl = 0, the pulse trains are decoded internally, but the microprocessor must implement the maintenance state as indicated by the maintenance in- terrupts (register mir0). if the optoin pin is being used for implementing maintenance functions, the iloss pin should not be used (i.e., it should be held high). instead, the iloss register bit should be used (register cfr0, bit 0). an internal 100 k w pull-up resistor is on this pin. 3 stled o status led driver. output pin for driving an led (source/sink 4.0 ma) that indicates the device status. the four defined states are low, high, 1 hz flashing, and 8 hz flashing (flashing occurs at 50% duty cycle). see the stled description section for a detailed explanation of these states. also, this pin indicates device sanity upon power on/reset, as follows: n if autoact/sck = 0 (pin 15) after a device reset (which sets auto- act = 0 in register gr0 bit 6, turning on autoactivation), stled will tog- gle at an 8 hz rate for at least 0.5 s, signifying an activation attempt. if the activation attempt succeeds, it will continue to ?sh per the normal start- up sequence (see stled description section). n if autoact/sck = 1 (pin 15) after a device reset, stled will go low for 1 s (?sh of life), indicating that the device is operational, and no acti- vation attempt will be made. 4 syn8k/lbind/fs o synchronous 8 khz clock or loopback indicator. if tdmen = 1 (register gr2, bit 5, default), the pin function is determined based on the state of pin 12 (syn8k_ctl/sdi) at the most recent rising edge of reset . as syn8k (syn8k_ctl/sdi = 0 at reset rising edge), this pin is an 8 khz 50% duty cycle clock that is synchronous with the recovered timing from the u-inter- face. when u-interface synchronization is not present, syn8k is free- running. as lbind (syn8k_ctl/sdi = 1 at reset rising edge), this pin in- dicates a 2b+d loopback: 0?o loopback. 1?oc requested 2b+d loopback in progress. frame strobe. if tdmen = 0, this pin is a programmable strobe output used to indicate appearance of b- and/or d-channel data on the tdm bus. polar- ity, offset, and duration of fs are programmable through the microprocessor interface (see register tdr0). fs will be disabled until at least one of bits 2? in register dfr1 is enabled.
data sheet january 1998 t7256 single-chip nt1 (scnt1) transceiver lucent technologies inc. 7 pin information (continued) table 1. pin descriptions (continued) * i u = input with internal pull-up; i d = input with internal pull-down. pin symbol type* name/function 5, 13 v ddd digital power. 5 v 5% power supply pins for digital circuitry. 6 iloss i u insertion loss test control (active-low) . the iloss pin is used to control sn1 tone transmission for maintenance. the optoin and iloss pins should not be used at the same time (i.e., optoin should be held high when iloss is active). this pin would typ- ically be used if an external ansi maintenance decoder is being used, in which case the decoder output drives the iloss pin. the iloss pin is ignored, and the functionality is controlled by the iloss bit (register cfr0, bit 0) if autoctl = 0 (register gr0, bit 3). internal 100 k w pull-up resistor on this pin. 0? transmitter sends sn1 tone continuously. 1?o effect on device operation. 7 fte/ tdmdi i u fixed/adaptive timing mode select. if tdmen = 1 (register gr2, bit 5, default), selects s/t-interface timing recovery mode: 0?ixed timing recovery mode. 1?daptive timing recovery mode. tdm data in. if tdmen = 0, this pin is the tdm bus 2b+d data input synchronous with tdmclk, and the s/t-interface timing mode is controlled via the ft bit (register gr2, bit 0). an internal 100 k w pull-up resistor is on this pin. 8 ps2e/ tdmdo i d /o power status #2. if tdmen = 1 (register gr2, bit 5, default), this is an input for the ps2 bit in transmit u-interface data stream. see ps2 bit description (register gr1, bit 1) for ps1 and ps2 message definition. an internal 100 k w pull-down resistor is on this pin. tdm data out. if tdmen = 0, this pin is the 2.048 mhz tdm bus 2b+d data output synchronous with tdmclk, and ps2 is controlled via the ps2 (register gr1, bit 1) mi- croprocessor register bit. 9 ps1e/ tdmclk i d /o power status #1. if tdmen = 1 (register gr2, bit 5, default), this is an input for the ps1 bit in transmit u-interface data stream. see ps2 bit description (register gr1, bit 1) for ps1 and ps2 message definition. if ps1e is not driven by an external control circuit, it must be pulled up externally with a 10 k w or less resistor to indicate the pres- ence of primary power. an internal 100 k w pull-down resistor is on this pin. tdm clock. if tdmen = 0, this pin is the 2.048 mhz tdm clock output synchronous with u-interface (if active) or is free-running, and ps1 is controlled via the ps1 micro- processor register bit. tdmclk will be disabled until at least one of bits 2? in register dfr1 is enabled.
data sheet t7256 single-chip nt1 (scnt1) transceiver january 1998 8 lucent technologies inc. pin information (continued) table 1. pin descriptions (continued) * i u = input with internal pull-up; i d = input with internal pull-down. pin symbol type* name/function 11 actmode/ int i u /o act bit mode. upon exiting reset , the state of actmode/int is read and if actmode/int = 1 (default), bit actsel = 1 (register gr2, bit 6). if actmode/ int = 0 (externally pulled down), then actsel = 0. an internal 100 k w pull-up re- sistor is on this pin. serial interface microprocessor interrupt (active-low). interrupt output for mi- croprocessor. any active, unmasked bit in interrupt registers uir0, sir0, or mir0 will cause int to go low. the bits in the interrupt registers uir0, sir0, and mir0 will be set on a true condition, independent of the state of the corresponding mask bits. if a masked, active interrupt bit is subsequently unmasked, the int pin will go low to indicate an interrupt for that condition. reading uir0, sir0, or mir0 clears the entire register and forces int high for 50 m s. after this interval, int will again reflect the state of any unmasked bit in these registers. the global interrupt register (giro) provides a summary status of the uir0, sir0, and mir0 interrupt registers and indicates if one of the registers currently has an active, unmasked interrupt bit. 12 syn8k_ctl /sdi i d syn8k/lbind control. if this pin is low at the rising edge of reset , the syn8k/ lbind/fs pin performs the syn8k function. otherwise, the pin performs the lbind function. an internal 100 k w pull-down resistor is on this pin. serial interface data input. data input for microprocessor interface. 14 sdo o serial interface data output. data output for microprocessor interface. this pin is 3-stated at all times except for when a microprocessor read from the t7256 is taking place. 15 autoact/ sck i d automatic activation. if this pin is low at the rising edge of reset , the autoact bit is written to 0, creating an activation attempt (see autoact [register gr0, bit 6] description in table 4). if pin is held high during external reset , no activation is attempted. an internal 100 k w pull-down resistor is on this pin. serial interface clock. clock input for microprocessor interface. 17 ckout o clock output. clock output function to drive other board components. powerup de- fault state is high-impedance to minimize power consumption. programmable via microprocessor register (register gr0, bits 1 and 2) to provide 15.36 mhz output or 10.24 mhz output. if u-interface is active, the 10.24 mhz output is synchronous with u-interface timing. 18 gnd o crystal oscillator ground. ground lead for crystal oscillator. 19 v ddo crystal oscillator power. power supply lead for crystal oscillator. 20 x1 o crystal #1. crystal connection #1 for 15.36 mhz oscillator. 21 x2 i crystal #2. crystal connection #2 for 15.36 mhz oscillator. 22, 33, 39, 42 v dda analog power. 5 v 5% power supply leads for analog circuitry. 23 tnr o transmit negative rail for s/t-interface. negative output of s/t-interface analog transmitter. connect to transformer through a 121 w 1% resistor. 24 tpr o transmit positive rail for s/t-interface. positive output of s/t-interface analog transmitter. connect to transformer through a 121 w 1% resistor.
data sheet january 1998 t7256 single-chip nt1 (scnt1) transceiver lucent technologies inc. 9 pin information (continued) table 1. pin description (continued) * i u = input with internal pull-up; i d = input with internal pull-down. pin symbol type* name/function 25, 34, 40, 41 gnd a analog ground. ground leads for analog circuitry. 26 rnr i receive negative rail for s/t-interface. negative input of s/t-interface analog re- ceiver. connect to transformer through a 10 k w 10% resistor. 27 rpr i receive positive rail for s/t-interface. positive input of s/t-interface analog re- ceiver. connect to transformer through a 10 k w 10% resistor. 28 vrcm common-mode voltage reference for u-interface circuits. connect a 0.1 m f 20% capacitor to gnd a (as close to the device pins as possible). 29 vrp positive voltage reference for u-interface circuits. connect a 0.1 m f 20% ca- pacitor to gnd a (as close to the device pins as possible). 30 vrn negative voltage reference for u-interface circuits. connect a 0.1 m f 20% ca- pacitor to gnd a (as close to the device pins as possible). 31 hn i hybrid negative input for u-interface. connect directly to negative side of u-interface transformer. 32 lop o line driver positive output for u-interface. connect to the u-interface transformer through a 16.9 w 1% resistor. 35 lon o line driver negative output for u-interface. connect to the u-interface transform- er through a 16.9 w 1% resistor. 36 hp i hybrid positive input for u-interface. connect directly to positive side of u-interface transformer. 37 sdinn i sigma-delta a/d negative input for u-interface. connect via an 820 pf 5% capacitor to sdinp. 38 sdinp i sigma-delta a/d positive input for u-interface. connect via an 820 pf 5% capacitor to sdinn. 43 reset i d reset (active-low). asynchronous schmitt trigger input. reset halts data transmis- sion, clears adaptive filter coefficients, resets the u-transceiver timing recovery cir- cuitry, resets the s/t-interface transceiver, and sets all microprocessor register bits to their default state. during reset, the u-interface transmitter produces 0 v and the output impedance is 135 w at tip and ring. the reset pin can be used to implement quiet mode maintenance testing (refer to pin 2 for more description). the states of pins 11, 12, and 15 (actmode/int , syn8k_ctl/sdi, and autoact/sck, respec- tively) are latched on the rising edge of reset . (see corresponding pin descriptions.) an internal 100 k w pull-down resistor is on this pin. reset must be held low for 1.5 ms after power on. device is fully functional after an additional 1 ms. 44 highz i u high-impedance control (active-low). control of the high-impedance function. an internal 100 k w pull-up resistor is on this pin. note: this pin does not 3-state the an- alog outputs. 0?ll digital outputs enter high-impedance state. 1?o effect on device operation.
data sheet t7256 single-chip nt1 (scnt1) transceiver january 1998 10 lucent technologies inc. application overview the t7256 is intended for use in isdn networks as part of a 2-wire to 4-wire converter (nt1) or as part of a termi- nal adapter (ta), providing 2-wire termination of the network with available voice and/or data ports. local switching of terminal voice/data is also supported by the t7256. figure 3 shows the nt1 and ta applications. see using the t7256 in a combination te/ta environment in the application briefs section for a detailed explanation of an appli- cation that has both te and ta functions. 5-2293 (c) figure 3. applications of t7256 t7256 4-wire s/t 2-wire 2b1q isdn line card lt network termination (nt1) switching system t7256 voice/data ports 2-wire 2b1q isdn line card lt terminal adapter (ta) voice/ data logic isdn te (terminal equipment) terminal (e.g., rs?32) and pots connections
data sheet january 1998 t7256 single-chip nt1 (scnt1) transceiver lucent technologies inc. 11 functional overview the t7256 device provides four major interfaces for information transfer: the u-interface, the s/t-interface, the microprocessor interface, and the time-division multiplexed (tdm) bus interface (see figure 1). use of the microprocessor and tdm bus interface is optional. if the microprocessor and tdm interfaces aren? required, the t7234 scnt1 euro-lite may be a more cost-effective solution (see the t7234 scnt1 euro- lite single-chip nt1 data sheet). similarly, if an s/t- interface is not required, the t7237 may be a more cost-effective solution (see the t7237 isdn u-interface transceiver data sheet). these devices are pin-com- patible with the t7256, but have a reduced feature set for cost-sensitive applications that don? require the full feature set of the t7256. routing of data between the s/t, u, and tdm inter- faces is controlled by the data ?w matrix that uses register settings accessible via the microprocessor port. the data ?w matrix circuitry routes 2b+d infor- mation between the appropriate interfaces, under direction of the microprocessor register settings. rout- ing between the t7256 interfaces allows con?urations to support both nt1 and ta applications. the architecture of the t7256 allows for a ?xible com- bination of automatically and manually controlled func- tions. a control ?w state machine, eoc state machine, and multiframing controller can be independently enabled or disabled. when enabled, these circuit blocks automatically perform their functions while ignoring the associated control bits in the microproces- sor registers. when disabled, the control bits are made available to the microprocessor for manipulation. at all times, the status bits are available to the microproces- sor and the 2b+d data can be routed via the data ?w matrix. the microprocessor interface is a serial communica- tions port consisting of input data (sdi), output data (sdo), input clock (sck), and an output interrupt pin (int ). the microprocessor interface supports synchro- nous communication between the t7256 and an inex- pensive microprocessor with a serial port. the interrupt is maskable via the onboard microprocessor interrupt mask registers. the internal register set controls vari- ous functions including information routing between interfaces, auto-eoc processing, maintenance testing, s/t-interface timing recovery mode, s- and q-channel processing, microprocessor interrupt masks, activation of the tdm bus, and frame strobe timing. the tdm interface consists of a tdm bus data clock (tdmclk), input data (tdmdi), output data (tdmdo), and frame strobe (fs). the 2b+d data is transmitted and received in ?ed time slots on the tdm bus; how- ever, the frame strobe output lead is programmable to support a wide variety of devices (codecs, hdlc pro- cessors, asynchronous interfaces) for direct connection on the tdm bus. the tdm bus exists as a selectable option via the microprocessor interface. when the tdm bus is activated, pins 4, 7, 8, and 9 are recon?ured to form the bus interface. the eoc state machine, when enabled, automatically performs the eoc channel functions as described in the ansi requirements. when disabled, control of the eoc channel is passed to the microprocessor via the appro- priate microprocessor register bits. the ansi maintenance controller can operate in fully automatic or in fully manual mode. in automatic mode, the device decodes and responds to mainte- nance states according to the ansi requirements. in manual mode, the device is controlled by an external maintenance decoder that drives the reset and iloss pins to implement the required maintenance states. the multiframing controller, when enabled, allows the s and q channels on the s/t-interface to be manipulated by the microprocessor. when disabled, the s- and q- channel bits are automatically loaded with their default values for applications not supporting multiframing. the control ?w state machine performs the functions of reserved bit insertion, automatic implementation of the ansi maintenance state machine, and automatic prioritization of multiple requests, such as reset, activa- tion, maintenance, etc. some bits that are normally controlled by the control ?w state machine can be forced to their active state by writing the appropriate register (i.e., register gr1). when the control ?w state machine is disabled (via the autoctl bit in register gr0), the only change in the operation is that reserved bit control and ansi maintenance control are passed directly to the microprocessor via register cfr0.
data sheet t7256 single-chip nt1 (scnt1) transceiver january 1998 12 lucent technologies inc. functional overview (continued) when the t7256 is powered on and there is no activity on the s/t- or u-interfaces (i.e., no pending activation request), it automatically enters a low-power idle mode in which it consumes an average of 35 mw. this mode is exited automatically when an activation or u maintenance request occurs from either the micro- processor or the s/t- or u-interfaces. the t7256 pro- vides a board-level test capability that allows functional veri?ation. finally, an led driver output indicates the status of the device during operation. u-interface frame structure data is transmitted over the u-interface in 240-bit groups called u frames. each u frame consists of an 18-bit synchronization word or inverted synchronization word (sw or isw), 12 blocks of 2b+d data (216 bits), and six overhead bits (m bits). a u-interface super- frame consists of eight u frames grouped together. the beginning of a u superframe is indicated by the inverted sync word (isw). the six overhead bits (m1 m6) from each of the eight u frames, when taken together, form the 48 m bits. figure 4 shows how u frames, superframes, and m bits are arranged. of the 48 m bits, 24 bits form the embedded operations channel (eoc) for sending messages from the lt to the nt and responses from the nt to the lt. there are two eoc messages per superframe with 12 bits per eoc message (eoc1 and eoc2). another 12 bits serve as u- interface control and status bits (ucs). the last 12 bits form the cyclic redundancy check (crc) which is cal- culated over the 2b+d data and the m4 bits of the pre- vious superframe. figure 5 and table 2 show the different groups of bits in the superframe. 5-2476 (c) figure 4. u-interface frame and superframe u1 u2 u3 u4 u5 u6 u7 u8 u-interface m bits [48] u-frame span = 1.5 ms u-superframe span = 12 ms isw[18] (2b+d) x 12 [ 216 bits] m[6]
data sheet january 1998 t7256 single-chip nt1 (scnt1) transceiver lucent technologies inc. 13 u-interface frame structure (continued) figure 5. u-interface superframe bit groups bit assignments table 2. u-interface bit assignment * lt(nt). values in parentheses () indicate meaning at the nt. ? cso is ?ed at 0 by the device to indicate both cold and warm start capability. nib is ?ed at 1 by the device to indicate the link is normal. bit # 1?8 19?34 235 236 237 238 239 240 frame # sync 12(2b+d) m1 m2 m3 m4 m5 m6 1 isw 2b+d eoc1 control & status (ucs) 2 sw 3 crc 4 5 eoc2 6 7 8 bit # 1?8 19?34 235 236 237 238 239 240 frame # sync 12(2b+d) m1 m2 m3 m4 m5 m6 1 isw 2b+d eoc a1 eoc a2 eoc a3 act r 1, 5 r 1, 6 2 sw 2b+d eoc dm eoc i1 eoc i2 dea (ps1)* r 2, 5 febe 3 sw 2b+d eoc i3 eoc i4 eoc i5 r 3, 4 (ps2)* crc 1 crc 2 4 sw 2b+d eoc i6 eoc i7 eoc i8 r 4, 4 (ntm)* crc 3 crc 4 5 sw 2b+d eoc a1 eoc a2 eoc a3 r 5, 4 (cso)* ? crc 5 crc 6 6 sw 2b+d eoc dm eoc i1 eoc i2 r 6, 4 crc 7 crc 8 7 sw 2b+d eoc i3 eoc i4 eoc i5 uoa (sai)* crc 9 crc 10 8 sw 2b+d eoc i6 eoc i7 eoc i8 aib (nib)* crc 11 crc 12
data sheet t7256 single-chip nt1 (scnt1) transceiver january 1998 14 lucent technologies inc. s/t-interface frame structure the s/t-interface transfers its subscriber line 2b+d information as a 192 kbits/s full-duplex signal grouped into frames of 48 bits with a period of 250 m s, as speci- ?d in the itu-t i.430/ansi t1.605 standard. thirty-six of the 48 bits sent in each direction convey user infor- mation (two 8-bit occurrences of each of the two b channels, and four d-channel bits). the remaining 12 bits per frame are used for framing, control, dc bal- ance, and maintenance. the frame structures are shown in each direction in figure 6. in the bit stream transmitted from the terminal endpoint (te) to the network termination (nt), 4 bits are used for framing (f and fa, each with a dc balancing bit l), eight additional l bits are used to balance the 32 b- channel bits, and 4 bits are d-channel bits. for the nt-to-te transmission, 4 bits (f with dc balanc- ing bit l, fa, and n) are used for framing, one m bit marks the start of a 20-frame multiframe, four e bits form an echo channel for retransmission of the d-chan- nel bits received from the te, one additional l bit is used to balance the contents of the entire frame, and 1 bit (a) is set to one when bit synchronization is achieved between te and nt as part of the info 4 state. one s bit is used for transmitting s subchannel messages in an nt-to-te multiframe. the framing procedure uses bipolar line-code viola- tions to establish synchronization. since the last binary 0 of any frame is a positive pulse and the f bit is also de?ed to be a positive pulse (see figure 7), the ?st bit of each frame represents a coding violation. in addi- tion, the second bit of each frame, a balance bit, is a negative pulse, and the next binary 0 in the frame is forced to be negative, causing another violation. both bipolar violations allow framing and provide dc balance. all other pulses follow the alternating convention. 5-2479 (c) figure 6. frame structures of nt and te frames fl eight b1 bits ld lfal eight b2 bits eight b1 bits eight b2 bits ldl ldl ldl nt-to- te frame te-to- nt frame fl eight b1 bits edafan eight b2 bits eight b1 bits eight b2 bits edm eds ed l one frame = 48 bits in 250 m s bandwidth = 192 kbits/s
data sheet january 1998 t7256 single-chip nt1 (scnt1) transceiver lucent technologies inc. 15 s/t-interface frame structure (continued) in the te-to-nt direction, in at least four of ?e frames, this second violation occurs within 13 bits of the f bit. if this coding algorithm is not maintained, the receiver loses synchronization, but the t7256 continues transmitting. f = framing bit fa = auxiliary framing bit or q-channel bit m = multiframe synchronization bit l = dc balancing bit n = bit set to binary value n = fa b1 = bit within b channel 1 d = d-channel bit a = activation bit b2 = bit within b channel 2 e = echo d-channel bit s = s-channel bit 5-2480 (c) figure 7. details of nt and te frames signals from nt to te signals from te to nt info 0 no signal. info 0 no signal. info 2 frame with all bits of b, d, and d echo (e) channels set to binary zero; bit a set to binary zero; n and l bits set ac- cording to the normal coding rules. info 1 a continuous signal with the following pattern: positive zero, negative zero, six ones. info 4 frames with operational data on b, d, and e channels; bit a set to binary one. info 3 synchronized frames with operational data on b and d channels. 48 1 +0 4 48 1 2 3 9 10 11121314 151617 232425 262728 343536373839 454647 48 1 b1 l f l b1 b1 b1 e d a fa n b2 b2 b2 e d m b1 b1 b1 e d s b2 b2 b2 e d l f l multiframe sync bit (optional, once in 20 frames) (nt to te) 2 10 11 12 13 14 15 23 24 25 26 34 35 36 37 45 46 47 b1 d f b1 l d l fa l b2 l d l b1 l d l b2 b2 l d l 1 ? l 3 4 16 17 b2 b2 27 28 b1 b1 38 39 b2 48 fa/n bit pair invert to flag q-bit transmission (te to nt) q-bit option (every 5th frame) 2-bit offset 48 bits in 250 m s time
data sheet t7256 single-chip nt1 (scnt1) transceiver january 1998 16 lucent technologies inc. s/t-interface frame structure (continued) the t7256 supports multiframing on the s/t-interface in conjunction with an external microprocessor that is used to enable multiframing and transmit and receive s- and q-channel messages. when multiframing is enabled, the m bit in the nt-to-te direction is set to a one every 20 frames and the fa bit is set to one every ?e frames. the te recognizes these states and, in returned frames immediately corresponding to those in which the nt set the fa bit, replaces the fa bit it sends to the nt with a q bit (q1 through q4). q1 is returned for each frame in which both the m and fa bits were set to one by the nt, with q2 through q4 following at ?e- frame intervals. (see figure 8.) the s-bit position in the nt-to-te direction is divided into ?e 4-bit subchannels during multiframing: sc1 sc5. message sets for subchannels sc3?c5 are not currently de?ed, and a message set for sc2 is de?ed only in ansi t1.605, but not itu i.430 (see the s/t-interface multiframing controller description sec- tion for more details). figure 8 indicates the location of the various s-subchannel bits during multiframing. 5-2481.b (c) figure 8. multiframing? subchannels and q subchannels 9 19 5 4 20 1 2 3 7 8 10 11 12 13 14 15 18 19 20 12 19 6 16 17 5 4 20 2 3 7 8 10 11 12 13 14 15 18 19 20 12 19 6 16 17 fa = 1 fa = 1 fa = 1 fa = 1 fa = 1 fa = q1 fa = q2 fa = q3 fa = q4 fa = q1 (nt to te) m bit = 1 in frame #1 marks start of multiframe (te to nt) the te-to-nt transmission has a nominal 2-bit delay relative to the nt-to-te frames. s bits occur in bit 37 of each nt-to-te frame. s-subchannel #1 bits sc11, sc12, sc13, and sc14 appear in frames 1, 6, 11, and 16. s-subchannel #2 bits sc21, sc22, sc23, and sc24 appear in frames 2, 7, 12, and 17. q bits occur every five frames. there are four q bits per multiframe in the fa bit position (bit 14) of frames 1, 6, 11, and 16. 20-frame multiframe
data sheet january 1998 t7256 single-chip nt1 (scnt1) transceiver lucent technologies inc. 17 u-interface description at the u-interface, the t7256 conforms to ansi t1.601 and etsi etr 080 when used with the proper line interface circuitry. the t7256 reference circuit description in the application briefs section of this doc- ument describes a detailed example of a u-interface circuit design. the 2b1q line code provides a four-level (quaternary) pulse amplitude modulation code with no redundancy. data is grouped into pairs of bits for conversion to qua- ternary (quat) symbols. figure 9 shows an example of this coding method. the u-interface transceiver section provides the 2b1q line coder (d/a conversion), pulse shaper, line driver, ?st-order line balance network, clock regeneration, and sigma-delta a/d conversion. the line driver, when connected to the proper transformer and interface cir- cuitry, generates pulses which meet the required 2b1q templates. the a/d converter is implemented by using a double-loop, sigma-delta modulator. the u transceiver block also takes input from the data ?w matrix and formats this information for the u-inter- face (see figure 1). during this formatting, synchroni- zation bits for u framing are added and a scrambling algorithm is applied. this data is then transferred to the 2b1q encoder for transmission over the u-interface. signals received from the u-interface are ?st passed through the sigma-delta a/d converter, and then sent to the digital signal processor for more extensive signal processing. the block provides decimation of the sigma-delta output, linear and nonlinear echo cancella- tion, automatic gain control, signal detection, phase shift interpolation, decision feedback equalization, tim- ing recovery, descrambling, and line-code polarity detection. the decision feedback equalizer circuit pro- vides the functionality necessary for proper operation on subscriber loops with bridged taps. a crystal oscillator provides the 15.36 mhz master clock for the device. the on-chip, phase-locked loop provides the ability to synchronize the chip to the line rate. the u-interface provides rapid cold start and warm start operation. from a cold start, the device is typically operational within four seconds. the interface supports activation/deactivation, and when properly deactivated, it stores the adaptive ?ter coef?ients permitting a warm start on the next activation request. a warm start typically requires 200 ms for the device to become operational. 5-2294 (c) figure 9. u-interface quat example ? 01 +3 10 +1 11 ? 00 ? 00 +1 11 +3 10 ? 00 ? 01 ? 01 +1 11 ? 01 ? 00 +3 10 +3 10 ? 01 +1 11 +3 +1 ? ? quat symbol bit coding
data sheet t7256 single-chip nt1 (scnt1) transceiver january 1998 18 lucent technologies inc. s/t-interface description at the s/t-interface, the 4-wire line transceiver meets the ansi t1.605 standard, itu-t i.430 recommenda- tion, and etsi ets 300 012 when used with the proper line interface circuitry. refer to the march 1996, t7903 isa multiport wide area connection (isa-mwac) device data sheet (ds96-084isdn). appendix f of the isa-mwac data sheet is an application brief that contains detailed information concerning guidelines for s/t line interface circuit design. the s/t transceiver interprets the frames received from the line and generates frames to be transmitted onto the s/t link. it exchanges full-duplex 2b+d information with the data ?w matrix. the transceiver consists of two sections, the transmitter and the receiver. the transmitter is a voltage-limited current source. the transmitted bits are timed by an internal 192 khz clock derived from the u-interface. the transmitter employs a line coding technique referred to in the standards as ?seudo-ternary coding with 100% pulse width, which is often referred to as alternate space inversion (asi) coding. asi coding rep- resents a logical 1 by the absence of a pulse and a log- ical 0 by alternating positive and negative pulses. asi is a differential strategy, with positive and negative rails connecting to the transformer. current ?ws through the transformer only when there is a voltage difference on the two rails. when a logical one or mark is being sent, meaning no current is desired, both rails go to a high-impedance condition. when a positive logical zero (space) is transmitted, the positive rail forces current to the negative rail through the transformer. the reverse occurs for a negative zero. table 3 and figure 10 illus- trate the asi coding method. table 3. line transmission code * z = high impedance. the line receiver is more complex. since the loop length to the subscriber(s) is variable, as is the number of tes on the loop (1 to 8), the receiver must be suf? ciently intelligent to adjust for widely varying input waveforms. the receiver uses a self-adjusting voltage threshold comparator to adapt to various loop lengths. it also features a digital timing recovery circuit employ- ing either adaptive or ?ed timing modes. the adaptive timing mode can be used on any loop con?uration (point-to-point, extended passive bus, short passive bus) in which round trip delays are between 0 m s and 42 m s and differential delays between tes are between 0 m s and 3.1 m s. this exceeds the requirement in the standards, which is 0? m s (see, for example, itu-t i.430 section a.2.1.3 (p. 58). a differential delay of 0 m s is meaningful in the case of a line transmitter and line receiver directly con- nected externally in a loopback con?uration, so the receiver can extract the 2b+d information correctly from the transmitted stream. a short passive bus configuration permits tes to be connected anywhere along the full length of the cable, with the restriction that the total round trip delay must be between 10 m s and 14 m s for all tes. thus, worst-case differential delay between tes can be as much as 4 m s. if the differential delay is more than 3.1 m s, adaptive tim- ing mode cannot be used. a fixed timing mode is avail- able for this case. when using fixed timing, the input stream is sampled 4.2 m s after the leading edge of each 192 khz transmit bit interval. the fixed/adaptive timing mode is controlled via the fte pin if the tdm highway is not enabled (tdmen = 0 in register gr2, bit 5). oth- erwise, it is controlled via the ft microprocessor bit (register gr2, bit 0). 5-2295 (c) figure 10. s/t-interface asi example microprocessor interface description the microprocessor interface, used to control and monitor the device, is compatible with most general- purpose serial microprocessor interfaces using a syn- chronous mode of transmission. a detailed description of the operation follows, and detailed timing information is given in the timing characteristics section. registers the on-chip registers are divided by major circuit block and by status and control function. microprocessor reg- ister control bits associated with the control ?w state machine, eoc state machine, and multiframing control- ler are ignored when those blocks are enabled (the device controls the blocks automatically). when the blocks are disabled, the control bits are used to drive device operations. the functional summary of the reg- isters and bits is shown in figure 11. positive rail negative rail current logic z* z* 0 1 1 0 +1 +0 0 1 ? ? 101 0 01 1 0
data sheet january 1998 t7256 single-chip nt1 (scnt1) transceiver lucent technologies inc. 19 microprocessor interface description (continued) registers (continued) figure 11. functional register map (addresses and bit assignments) function add- ress reg- ister r/w bit 765 4 3210 global device control?evice configuration 00h gr0 r/w rsv autoact multif autoeoc autoctl crate1 crate0 reset global device control? u-interface 01h gr1 r/w sai1 sai0 xpcy actt ntm ps1 ps2 lpbk global device control? s/t-interface 02h gr2 r/w stoa actsel tdmen u2bdln sxe sreset spwrud ft data flow control? & s/t b channels 03h dfr0 r/w sxb21 sxb20 sxb11 sxb10 uxb21 uxb20 uxb11 uxb10 data flow control? chan- nels & tdm bus 04h dfr1 r/w tdmdu tdmb2u tdmb1u tdmds tdmb2s tdmb1s sxd uxd tdm bus timing control 05h tdr0 r/w fsp fsc2 fsc1 fsc0 control flow st. mach. control? mainten./rsv. bits 06h cfr0 r/w r64t r25t r16t r15t afrst iloss control flow st. mach. status 07h cfr1 r i4i aib febe nebe uoa oof xact actr control flow st. mach. status? reserved bits 08h cfr2 r r64r r54r r44r r34r r25r r16r r15r eoc state machine control?ddress 09h ecr0 r/w ccrc u2bdlt ub2lp ub1lp dmt a1t a2t a3t eoc state machine control? information 0ah ecr1 r/w i1t i2t i3t i4t i5t i6t i7t i8t eoc state machine status?ddress 0bh ecr2 r dmr a1r a2r a3r eoc state machine status? information 0ch ecr3 r i1r i2r i3r i4r i5r i6r i7r i8r q channel bits 0dh mcr0 r q1 q2 q3 q4 s subchannel 1 0eh mcr1 r/w sc11 sc12 sc13 sc14 s subchannel 2 0fh mcr2 r/w sc21 sc22 sc23 sc24 s subchannel 3 10h mcr3 r/w sc31 sc32 sc33 sc34 s subchannel 4 11h mcr4 r/w sc41 sc42 sc43 sc44 s subchannel 5 12h mcr5 r/w sc51 sc52 sc53 sc54 u-interface inter- rupt register 13h uir0 r tsfint rsfint ousc berr actsc eocsc u-interface inter- rupt mask register 14h uir1 r/w tsfintm rsfintm ouscm berrm actscm eocscm s/t-interface inter- rupt register 15h sir0 r i4c sfecv qsc som s/t-interface inter- rupt mask register 16h sir1 r/w i4cm sfecvm qscm somm maintenance inter- rupt register 17h mir0 r emint ilint qmint maintenance inter- rupt mask register 18h mir1 r/w emintm ilintm qmintm global interrupt register 19h gir0 r mint sint uint
data sheet t7256 single-chip nt1 (scnt1) transceiver january 1998 20 lucent technologies inc. microprocessor interface description (continued) registers (continued) table 4. global device control?evice con?uration (address 00h) reg r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 gr0 r/w rsv. autoact multif autoeoc autoctl crate1 crate0 reset default state on reset 1 autoact/ sck 11 1111 register bit symbol name/description gr0 0 reset reset. same function as external reset pin, except the state of the autoact/ sck, actmode/int , and syn8k_ctl/sdi pins are not checked. assertion of this bit halts data transmission, clears adaptive filter coefficients, resets the s/t- interface transceiver, and sets all microprocessor register bits (except itself) to their default state. the microprocessor must write this bit back to a 1 to bring the t7256 out of its reset state. during reset, the u-interface transmitter produces 0 v and the output impedance is 135 w at tip and ring. 0?eset. 1?o effect on device operation (default). gr0 2? crate[1:0] ckout rate control. 00?ot used. 01?0.24 mhz synchronous with u-interface (if active); otherwise, free- running. 10?5.36 mhz free-running. 11?-state (default). gr0 3 autoctl auto control enable. enables automatic control of ansi maintenance and re- served bit insertion. when autoctl = 1, register cfr0 is ignored and the con- trol flow state machine automatically controls ansi maintenance functions and reserved bit insertion. when autoctl = 0, the microprocessor controls ansi maintenance functions and reserved bit insertion via register cfr0. 0?fr0 functions controlled manually by microprocessor. 1?fr0 functions controlled automatically. gr0 4 autoeoc automatic eoc processor enable. enables eoc state machine which imple- ments eoc processing per the ansi standard. when autoeoc = 1, registers ecr0?cr1 are ignored. the eoc state machine only responds to addresses 000 and 111 as valid addresses. 0?oc state machine disabled. 1?oc state machine enabled (default). gr0 5 multif multiframing control. enables the multiframing controller and allows the micro- processor to access the s and q channels. when disabled, multiframing is not implemented (the nt transmits all 0s in the fa and m bit positions and all 1s in the s bit positions to the te). also, register bits 3? in mcr0 are forced to 1 and register bits 3? in mcr1? are forced to 0 when multiframing is disabled. 0?ultiframing controller enabled. 1?ultiframing controller disabled (default).
data sheet january 1998 t7256 single-chip nt1 (scnt1) transceiver lucent technologies inc. 21 microprocessor interface description (continued) registers (continued) table 4. global device control?evice configuration (address 00h) (continued) register bit symbol name/description gr0 6 autoact automatic activation control. upon a 1-to-0 transition of the autoact bit, the control flow state machine attempts one activation of the u-interface. after the acti- vation attempt, this bit is internally set to 1, automatically. if the autoact/sck pin is low on the rising edge of reset , autoact is written to 0 and one activation at- tempt is made (see autoact/sck pin description in table 1). multiple activation at- tempts can be made by repeatedly writing 0s to this bit. 1?o activation attempt. 0?ne activation attempt. gr0 7 reserved. set to 1. 1?efault.
data sheet t7256 single-chip nt1 (scnt1) transceiver january 1998 22 lucent technologies inc. microprocessor interface description (continued) registers (continued) table 5. global device control?-interface (address 01h) reg r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 gr1 r/w sai1 sai0 xpcy actt ntm ps1 ps2 lpbk default state on reset 11101111 register bit symbol name/description gr1 0 lpbk u-interface analog loopback. controls loopback of u-interface data stream at the line interface. loopback turns off the echo canceler and re- configures the receive scrambler to match the transmit scrambler. the line should be disconnected before this loopback test. this ensures that a suf- ficiently large echo is generated so that the device can detect the echo as received data and synchronize to it. 0?-interface analog loopback. 1?o effect on device operation (default). gr1 1 ps2 power status #2. controls ps2 bit in transmit u-interface data stream if tdmen = 0 (register gr2, bit 5). if tdmen = 1, ps2 bit is ignored. for ansi t1.601 applications, ps1 and ps2 indicate the nt power status via the following messages: ps1 ps2 power status 0 0 dying gasp. 0 1 primary power out. 1 0 secondary power out. 1 1 all power normal (default). gr1 2 ps1 power status #1. controls ps1 bit in transmit u-interface data stream if tdmen = 0 (register gr2, bit 5). if tdmen = 1, ps1 bit is ignored. see ps2 bit definition. gr1 3 ntm nt test mode. controls ntm bit in transmit u-interface data stream and indicates if the nt is in a customer-initiated test mode. 0?t is currently in a customer-initiated test mode. 1?o effect on device operation (default). gr1 4 actt transmit activation. controls act bit in transmit u-interface data stream. 0?o effect on device operation (default). 1?eady to transmit. gr1 5 xpcy transparency. controls data being transmitted at u-interface. 0?nable data transparency. 1?o effect on device operation (default). gr1 7? sai[1:0] s/t-interface activity indicator control. controls sai bit in transmit u-interface data stream. for ansi t1.601 applications, the sai bit is set to 1 to indicate to the network that there is activity (info 1 or info 3) at the s/t reference point. otherwise, it is set to 0. the sai[1:0] bits provide the following options for controlling the sai bit: 00?orces sai to 0 on the u-interface. 01?orces sai to 1 on the u-interface. 1x?ai is set internally according to s-interface activity (default = 11).
data sheet january 1998 t7256 single-chip nt1 (scnt1) transceiver lucent technologies inc. 23 microprocessor interface description (continued) registers (continued) table 6. global device control?/t-interface (address 02h) reg r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 gr2 r/w stoa actsel tdmen u2bdln sxe sreset spwrud ft default state on reset 1 actmode/ int pin 1111 1 1 register bit symbol name/description gr2 0 ft fixed/adaptive timing control. controls mode of timing recovery on s/t-inter- face if tdmen = 0 (register gr2, bit 5). if tdmen = 1, ft is ignored. 0?ixed timing. 1?daptive timing (default). gr2 1 spwrud s/t-interface powerdown control. when 0, this bit forces the s/t-interface to remain in a powerdown mode. this is the same low-power mode the s/t-interface is in when the t7256 is in its idle state with no activity on the u- or s/t-interfac- es. in this mode, all s/t-interface circuits are powered down, except for circuits required to detect an activation request from a te. 0?owerdown. 1?ormal (default). gr2 2 sreset s/t-interface reset. while 0, this bit causes a reset of the s/t-interface, initial- izing the interface in the same manner as the external reset pin. must be set to 1 for normal operation. 0?eset. 1?ormal (default). gr2 3 sxe s/t-interface d-channel echo bit control. controls data in e channel from nt to te on s/t-interface. this bit must be cleared during 2b+d loopbacks to meet itu-t i.430 requirements. 0?ll 0s. 1?choes d channel from s/t receive path (default). gr2 4 u2bdln nontransparent 2b+d loopback control. when 0, this bit causes a nontrans- parent loopback of 2b+d data from u receiver to u transmitter upstream of the data flow matrix. note that this loopback path is not as close to the s/t-interface as the transparent loopback initiated by u2bdlt (register ecr0, bit 6). this loop- back may be useful for test purposes. when this bit is set, the upstream data (nt to lt direction) will be forced to all 1s until either actr = 1 (register cfr1, bit 0) or xpcy = 0 (register gr1, bit 5). 0?b+d loopback. all 1s 2b+d data is automatically generated towards the te. 1?o loopback (default). gr2 5 tdmen tdm bus select. selects functions of pins 4, 7, 8, and 9. 0?dm bus functions. pins 4, 7, 8, and 9 configured as fs, tdmdi, tdmdo, and tdmclk, respectively. see dfr1 and tdr0 registers for tdm bus programming details. microprocessor register bits gr11, gr12, and gr20 control the ps2, ps1, and ft functions. 1?o tdm bus. pins 4, 7, 8, and 9 configured as syn8k/lbind, fte, ps2e, and ps1e, respectively (default).
data sheet t7256 single-chip nt1 (scnt1) transceiver january 1998 24 lucent technologies inc. microprocessor interface description (continued) registers (continued) table 6. global device control?/t-interface (address 02h) (continued) reg r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 gr2 r/w stoa actsel tdmen u2bdln sxe sreset spwrud ft default state on reset 1 actmode/ int pin 1111 1 1 register bit symbol name/description gr2 6 actsel act mode select. controls the state of the transmitted act bit when an eoc loopback 2 (2b+d loopback) is requested. the loopback 2 occurs automatical- ly if autoeoc = 1 (register gr0, bit 4). otherwise, bit u2bdlt (register ecr0, bit 6) must be set to 0. the loopback is accomplished in the device by looping the output of the s/t transmitter back to the input of the s/t receiver at the device pins (i.e., as close to the s/t-interface as possible). the s/t transceiver will ignore any signals transmitted by the te, and the t7256 will synchronize to its own transmit signal causing info 3 to be reported. the ini- tial state of actsel is determined by the state of the actmode/int pin on the rising edge of reset . 0?ct = 0 during loopback 2 (per ansi t1.601). the data received at the nt is looped back towards the lt as soon as the 2b+d loopback is en- abled. 1?ct = 1 during loopback 2 after info 3 is recognized at the s/t-interface (per etsi etr 080). the data received by the nt is not looped back to- wards the lt until after act = 1 is received from the lt. prior to this time, 2b+d data toward the lt is all 1s. gr2 7 stoa s/t only activation. set to 0 to force an s/t activation when the u-interface is inactive. when the u-interface is active, this bit is ignored. stoa is reset to 1 upon the receipt of a u-interface tone, an info1 or info3 signal, or a 1-to- 0 transition of autoact (register gr0, bit 6). 0?ttempt an s/t only activation. 1?o effect on device operation (default).
data sheet january 1998 t7256 single-chip nt1 (scnt1) transceiver lucent technologies inc. 25 microprocessor interface description (continued) registers (continued) table 7. data flow control? and s/t b channels (address 03h) reg r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dfr0 r/w sxb21 sxb20 sxb11 sxb10 uxb21 uxb20 uxb11 uxb10 default state on reset 11111111 register bit symbol name/description dfr0 1? uxb1[1:0] u-interface transmit path source for b1 channel. refer to point #1 in figure 16. 00?ot used. 01?dm bus. 10?ll 1s. 11?/t-interface receive (default). dfr0 3? uxb2[1:0] u-interface transmit path source for b2 channel. refer to point #1 in figure 16. 00?ot used. 01?dm bus. 10?ll 1s. 11?/t-interface receive (default). dfr0 5? sxb1[1:0] s/t-interface transmit path source for b1 channel. refer to point #2 in figure 16. 00?ot used. 01?dm bus. 10?/t-interface receive (itu-t i.430 loop c for b1 channel). 11?-interface receive (default). dfr0 7? sxb2[1:0] s/t-interface transmit path source for b2 channel. refer to point #2 in figure 16. 00?ot used. 01?dm bus. 10?/t-interface receive (itu-t i.430 loop c for b2 channel). 11?-interface receive (default).
data sheet t7256 single-chip nt1 (scnt1) transceiver january 1998 26 lucent technologies inc. microprocessor interface description (continued) registers (continued) table 8. data flow control? channels and tdm bus (address 04h) bits 2? are enabled only if tdmen = 0 (register gr2, bit 5). the tdmclk and fs outputs are activated if any one of bits 2? is enabled. the tdmdo output is activated during time slots enabled by programming bits 2?. reg r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dfr1 r/w tdmdu tdmb2u tdmb1u tdmds tdmb2s tdmb1s sxd uxd default state on reset 11 111111 register bit symbol name/description dfr1 0 uxd u-interface transmit path source for d channel. refer to point #1 in figure 16. 0?dm bus. 1?/t-interface receive (default). dfr1 1 sxd s/t-interface transmit path source for d channel. refer to point #2 in figure 16. 0?dm bus. 1?-interface receive (default). dfr1 2 tdmb1s tdm bus transmit control for b1 channel from s/t-interface. refer to point #3 in figure 16. controls transmit time slot allocated on tdm bus for b1 channel derived from s/t-interface receiver. 0?ime slot enabled. 1?ime slot disabled (high impedance) (default). dfr1 3 tdmb2s tdm bus transmit control for b2 channel from s/t-interface. refer to point #3 in figure 16. controls transmit time slot allocated on tdm bus for b2 channel derived from s/t-interface receiver. 0?ime slot enabled. 1?ime slot disabled (high impedance) (default). dfr1 4 tdmds tdm bus transmit control for d channel from s/t-interface. refer to point #3 in figure 16. controls transmit time slot allocated on tdm bus for d channel derived from s/t-interface receiver. 0?ime slot enabled. 1?ime slot disabled (high impedance) (default). dfr1 5 tdmb1u tdm bus transmit control for b1 channel from u-interface. refer to point #3 in figure 16. controls transmit time slot allocated on tdm bus for b1 channel derived from u-interface receiver. 0?ime slot enabled. 1?ime slot disabled (high impedance) (default). dfr1 6 tdmb2u tdm bus transmit control for b2 channel from u-interface. refer to point #3 in figure 16. controls transmit time slot allocated on tdm bus for b2 channel derived from u-interface receiver. 0?ime slot enabled. 1?ime slot disabled (high impedance) (default). dfr1 7 tdmdu tdm bus transmit control for d channel from u-interface. refer to point #3 in figure 16. controls transmit time slot allocated on tdm bus for d channel derived from u-interface receiver. 0?ime slot enabled. 1?ime slot disabled (high impedance) (default).
data sheet january 1998 t7256 single-chip nt1 (scnt1) transceiver lucent technologies inc. 27 microprocessor interface description (continued) registers (continued) table 9. tdm bus timing control (address 05h) bits 0? are enabled only if tdmen = 0 (register gr2, bit 5) and one or more of bits dfr1[2:7] are set to 0. reg r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tdr0 r/w fsp fsc2 fsc1 fsc0 default state on reset 1111 register bit symbol name/description tdr0 2? fsc[2:0] frame strobe (fs) control. selects location of strobe envelope within tdm bus time slots. 000?/t-interface 2b+d channel strobe (18-bit envelope). 001?-interface 2b+d channel strobe (18-bit envelope). 010?/t-interface b2 channel strobe (8-bit envelope). 011?-interface b2 channel strobe (8-bit envelope). 100?/t-interface d channel strobe (2-bit envelope). 101?-interface d channel strobe (2-bit envelope). 110?/t-interface b1 channel strobe (8-bit envelope). 111?-interface b1 channel strobe (8-bit envelope) (default). tdr0 3 fsp frame strobe (fs) polarity. 0?ctive-low envelope. 1?ctive-high envelope (default).
data sheet t7256 single-chip nt1 (scnt1) transceiver january 1998 28 lucent technologies inc. microprocessor interface description (continued) registers (continued) table 10. control flow state machine control?aintenance/reserved bits (address 06h) this register has no effect on device operation if autoctl = 1 (register gr0, bit 3). reg r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cfr0 r/w r64t r25t r16t r15t afrst iloss default state on reset 111111 register bit symbol name/description cfr0 0 iloss insertion loss test control. the insertion loss test mode is initiated by setting afrst = 0 and iloss = 0, and then setting afrst = 1. when enabled, the u-interface transmitter continuously transmits the sequence sn1. the u-interface receiver remains reset. the u-interface transceiver performs an internal reset when the iloss bit returns to its inactive state. 0?-transmitter sends sn1 tone continuously. 1?o effect on device operation (default). cfr0 1 afrst adaptive filter reset. u-transceiver reset. assertion of this bit halts u- interface data transmission and clears adaptive filter coefficients. dur- ing afrst, the u transmitter produces 0 v and has an output imped- ance of 135 w . if the microprocessor interface is being used, the afrst bit should be used to place the device in quiet mode for u-interface maintenance procedures. assertion of afrst does not reset the s/t transceiver, microprocessor register bits, or the u-interface timing re- covery. 0?-transceiver reset. 1?o effect on device operation (default). cfr0 3? r[16:15]t transmit reserved bits. controls r 1, 6 and r 1, 5 in transmit u-interface data stream. 11?default.) cfr0 4 r25t transmit reserved bit. controls r 2, 5 in transmit u-interface data stream. 1?default.) cfr0 5 r64t transmit reserved bit. controls r 6, 4 in transmit u-interface data stream. 1?default.)
data sheet january 1998 t7256 single-chip nt1 (scnt1) transceiver lucent technologies inc. 29 microprocessor interface description (continued) registers (continued) table 11. control flow state machine status (address 07h) reg r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cfr1 r i4i aib febe nebe uoa oof xact actr register bit symbol name/description cfr1 0 actr receive activation. follows act bit in receive u-interface data stream. 0?ending activation. 1?eady to transmit. cfr1 1 xact u-transceiver active. 0?ransceiver not active. 1?ransceiver starting up or active. cfr1 2 oof out of frame. 0?-interface out of frame. 1?ormal. cfr1 3 uoa u-interface only activation. follows uoa bit in receive u-interface data stream. 0?-interface only for activation. 1?-interface and s/t-interface for activation. cfr1 4 nebe near-end block error. follows nebe bit in receive u-interface data stream. 0?rc error detected in previously received u frame. 1?o error. cfr1 5 febe far-end block error. follows febe bit in receive u-interface data stream. 0?rror detected at lt. 1?o error. cfr1 6 aib alarm indication bit. follows aib in receive u-interface data stream. 0?ailure of intermediate 2b+d transparent element. 1?ransmission path established between lt and nt. cfr1 7 i4i info 4 indicator. 0?on-info 4. 1?nfo 4.
data sheet t7256 single-chip nt1 (scnt1) transceiver january 1998 30 lucent technologies inc. microprocessor interface description (continued) registers (continued) table 12. control flow state machine status?eserved bits (address 08h) reg r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cfr2 r r64r r54r r44r r34r r25r r16r r15r register bit symbol name/description cfr2 1? r[16:15]r receive reserved bits. follows r 1, 5 and r 1, 6 in receive u-interface data stream. cfr2 2 r25r receive reserved bits. follows r 2, 5 in receive u-interface data stream. cfr2 6? r[64:54:44:34]r receive reserved bits. follows r 3, 4 ; r 4, 4 ; r 5, 4 ; and r 6, 4 in receive u- interface data stream.
data sheet january 1998 t7256 single-chip nt1 (scnt1) transceiver lucent technologies inc. 31 microprocessor interface description (continued) registers (continued) table 13. eoc state machine control?ddress (address 09h) this register has no effect on device operation if autoeoc = 1 (register gr0, bit 4). reg r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ecr0 r/w ccrc u2bdlt ub2lp ub1lp dmt a1t a2t a3t default state on reset 11111000 register bit symbol name/description ecr0 0? a[3:1]t transmit eoc address. 000?t address (default). 111?roadcast address. ecr0 3 dmt transmit eoc data or message indicator. 0?ata. 1?essage (default). ecr0 4 ub1lp u-interface loopback of b1 channel control. control for u-interface transparent b1 loopback. ub1lp and ub2lp may be enabled concurrent- ly. 0?1 channel loopback from u-interface receive to u-interface trans- mit upstream of data flow matrix. 1?o loopback (default). ecr0 5 ub2lp u-interface loopback of b2 channel control. control for u-interface transparent b2 loopback. ub1lp and ub2lp may be enabled concurrent- ly. 0?2 channel loopback from u-interface receive to u-interface trans- mit upstream of data flow matrix. 1?o loopback (default). ecr0 6 u2bdlt transparent 2b+d loopback control. when activated, this bit causes a transparent 2b+d loopback from s/t transmitter to s/t receiver at the device pins (i.e., as close as possible to the s/t-interface) according to itu-t i.430 loop2. any signals from the te are ignored during this loop- back. 0?ransparent 2b+d loopback: the microprocessor must clear the d-channel echo bit control (sxe = 0) and data flow matrix (sxb10 = sxb11 = sxb20 = sxb21 = sxd = uxb10 = uxb11 = uxb20 = uxb21 = uxd = 1) for proper operation of the loopback. 1?o loopback (default). ecr0 7 ccrc corrupt cyclic redundancy check. used to corrupt the crc informa- tion transmitted at the u-interface. 0?orrupt crc generation. 1?enerate correct crc (default).
data sheet t7256 single-chip nt1 (scnt1) transceiver january 1998 32 lucent technologies inc. microprocessor interface description (continued) registers (continued) table 14. eoc state machine control?nformation (address 0ah) this register has no effect on device operation if autoeoc = 1 (register gr0, bit 4). table 15. eoc state machine status?ddress (address 0bh) this register contains the currently received eoc address and data/message indicator bits independent of the state of autoeoc (register gr0, bit 4). table 16. eoc state machine status?nformation (address 0ch) this register contains the currently received eoc information bits independent of the state of autoeoc (register gr0, bit 4). reg r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ecr1 r/w i1t i2t i3t i4t i5t i6t i7t i8t default state on reset 11111111 register bit symbol name/description ecr1 0? i[8:1]t transmit eoc information. these bits are transmitted as the eoc chan- nel message when in manual eoc mode. see eoc state machine description section for a list of possible eoc messages. reg r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ecr2 r dmra1ra2ra3r register bit symbol name/description ecr2 0? a[3:1]r receive eoc address. these bits store the received eoc address. 000 = nt address. 001?10 = intermediate element addresses. 111 = broadcast address. ecr2 3 dmr receive eoc data or message indicator. 0?ata. 1?essage. reg r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ecr3 r i1r i2r i3r i4r i5r i6r i7r i8r register bit symbol name/description ecr3 0? i[8:1]r receive eoc information. receive eoc channel message or data.
data sheet january 1998 t7256 single-chip nt1 (scnt1) transceiver lucent technologies inc. 33 microprocessor interface description (continued) registers (continued) table 17. q-channel bits (address 0dh) these register bits are forced to 1 if multif = 1 (register gr0, bit 5) and during reset . table 18. s subchannels 1? (address 0eh?2h) these register bits have no effect on device operation and are set to 0 if multif = 1. refer to the s/t-interface multiframing controller description section for more detail on using s and q channels. reg r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mcr0 r q1q2q3q4 register bit symbol name/description mcr0 0? q[4:1] q-channel bits. four bits reflecting the four q bits (q1?4) received in the last completed multiframe. bits are loaded at the end of the mul- tiframe. reg r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mcr1 r/w sc11 sc12 sc13 sc14 mcr2 r/w sc21 sc22 sc23 sc24 mcr3 r/w sc31 sc32 sc33 sc34 mcr4 r/w sc41 sc42 sc43 sc44 mcr5 r/w sc51 sc52 sc53 sc54 default state on reset 0000 register bit symbol name/description mcr1 0? sc1[4:1] s subchannel 1. mcr2 0? sc2[4:1] s subchannel 2. mcr3 0? sc3[4:1] s subchannel 3. mcr4 0? sc4[4:1] s subchannel 4. mcr5 0? sc5[4:1] s subchannel 5.
data sheet t7256 single-chip nt1 (scnt1) transceiver january 1998 34 lucent technologies inc. microprocessor interface description (continued) registers (continued) table 19. u-interface interrupt register (address 13h) these bits are cleared during reset . reg r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 uir0 r tsfint rsfint ousc berr actsc eocsc register bit symbol name/description uir0 0 eocsc eoc state change on u-interface. activates (set to 1) when the re- ceived eoc message changes state. bit is cleared on read. see eoc state machine description section for details. 0?o change in eoc state. 1?oc state change. uir0 1 actsc activation/deactivation state change on u-interface. activates (set to 1) during changes in the status bits monitoring u-interface activation and deactivation (actr and xact, register cfr1, bits 0 and 1). bit cleared on read. 0?o activation/deactivation activity. 1?hange in state of activation/deactivation bits. uir0 2 berr block error on u-interface. activates (set to 1) when received signal contains either a near-end (nebe = 0) or a far-end (febe = 0) block er- ror. bit cleared on read. 0?o block errors. 1?lock error. uir0 3 ousc other u-interface state change. activates (set to 1) when any of the following bits change state: oof, uoa, aib, and rx, y (all reserved u- interface status bits). bit cleared on read. 0?o state change. 1?tate change. uir0 4 rsfint receive superframe interrupt. activates (set to 1) when the receive superframe boundary occurs. bit cleared on read. 0 to 1?irst 2b+d data of the receive u superframe. uir0 5 tsfint transmit superframe interrupt. activates (set to 1) when the transmit superframe boundary occurs. bit cleared on read. 0 to 1?irst 2b+d data of the transmit u superframe.
data sheet january 1998 t7256 single-chip nt1 (scnt1) transceiver lucent technologies inc. 35 microprocessor interface description (continued) registers (continued) table 20. u-interface interrupt mask register (address 14h) reg r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 uir1 r/w tsfintm rsfintm ouscm berrm actscm eocscm default state on reset 1 1 1 1 1 1 register bit symbol name/description uir1 0 eocscm eoc state change on u-interface mask. 0?ocsc interrupt enabled. 1?ocsc interrupt disabled (default). uir1 1 actscm activation/deactivation state change on u-interface mask. 0?ctsc interrupt enabled. 1?tcsc interrupt disabled (default). uir1 2 berrm block error on u-interface mask. 0?err interrupt enabled. 1?err interrupt disabled (default). uir1 3 ouscm other u-interface state change mask. 0?usc interrupt enabled. 1?usc interrupt disabled (default). uir1 4 rsfintm receive superframe interrupt mask. 0?sfint interrupt enabled. 1?sfint interrupt disabled (default). uir1 5 tsfintm transmit superframe interrupt mask. 0?sfint interrupt enabled. 1?sfint interrupt disabled (default).
data sheet t7256 single-chip nt1 (scnt1) transceiver january 1998 36 lucent technologies inc. microprocessor interface description (continued) registers (continued) table 21. s/t-interface interrupt register (address 15h) these bits are cleared during reset . table 22. s/t-interface interrupt mask register (address 16h) reg r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sir0 r i4c sfecv qsc som register bit symbol name/description sir0 0 som start of multiframe. activates (set to 1) upon transmission of the f bit that begins a multiframing interval toward the te. bit is cleared on read. 0 to 1?tart of multiframe. sir0 1 qsc q-bits state change. activates (set to 1) when the set of four q bits received in a multiframe differs from the set of q bits received in the previous multiframe. bit is cleared on read. 0?o state change. 1?tate change. sir0 2 sfecv s-channel far-end code violation. activates when an illegal line code violation or extra/missing bipolar violations are detected in the s/t-interface data stream. changes on multiframe boundary. only active if multif = 0 (register gr0, bit 5) and a transparent loop2 is not in effect. bit is cleared on read. 0?o code violations. 1?t least one code violation. sir0 3 i4c info 4 change. 0?o info 4 state change. 1?nfo 4 state change. reg r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sir1 r/w i4cm sfecvm qscm somm default state on reset 1 1 1 1 register bit symbol name/description sir1 0 somm start of multiframe mask. 0?om interrupt enabled. 1?om interrupt disabled (default). sir1 1 qscm q-bits state change mask. 0?sc interrupt enabled. 1?sc interrupt disabled (default). sir1 2 sfecvm s-subchannel far-end code violation mask. 0?fecvm interrupt enabled. 1?fecvm interrupt disabled (default). sir1 3 i4cm info 4 change mask. 0?4c interrupt enabled. 1?4c interrupt disabled (default).
data sheet january 1998 t7256 single-chip nt1 (scnt1) transceiver lucent technologies inc. 37 microprocessor interface description (continued) registers (continued) table 23. maintenance interrupt register (address 17h) these bits are cleared during reset . table 24. maintenance interrupt mask register (address 18h) reg r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mir0 r emint ilint qmint register bit symbol name/description mir0 0 qmint quiet mode interrupt. activates (set to 1) when the ansi maintenance state machine detects a request on the optoin pin for the device to en- ter the quiet mode. bit is cleared on read. 0?o quiet mode request. 1?uiet mode requested. mir0 1 ilint insertion loss interrupt. activates (set to 1) when the ansi mainte- nance state machine has detected a request on the optoin pin for the device to transmit the sn1 tone on the u-interface. bit is cleared on read. 0?o sn1 tone request. 1?n1 tone requested. mir0 2 emint exit maintenance mode interrupt. activates (set to 1) when the ansi maintenance state machine detects a request on the optoin pin for the device to exit the current maintenance mode. bit is cleared on read. 0?o exit request. 1?xit requested. reg r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mir1 r/w emintm ilintm qmintm default state on reset 1 1 1 register bit symbol name/description mir1 0 qmintm quiet mode interrupt mask. 0?mint interrupt enabled. 1?mint interrupt disabled (default). mir1 1 ilintm insertion loss interrupt mask. 0?lint interrupt enabled. 1?lint interrupt disabled (default). mir1 2 emintm exit maintenance mode interrupt mask. 0?mint interrupt enabled. 1?mint interrupt disabled (default).
data sheet t7256 single-chip nt1 (scnt1) transceiver january 1998 38 lucent technologies inc. microprocessor interface description (continued) registers (continued) table 25. global interrupt register (address 19h) these bits are cleared during reset . reg r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 gir0 r mint sint uint register bit symbol name/description gir0 0 uint u-transceiver interrupt. activates (set to 1) when any of the unmasked u-transceiver interrupt bits (register uir0) activate. 0?o u-transceiver interrupts. 1?-transceiver interrupt active. gir0 1 sint s/t-transceiver interrupt. activates (set to 1) when any of the un- masked s/t-transceiver interrupt bits (register sir0) activate. 0?o s/t-transceiver interrupts. 1?/t-transceiver interrupt active. gir0 2 mint maintenance interrupt. activates (set to 1) when any of the unmasked maintenance interrupt bits (register mir0) activate. 0?o maintenance interrupts. 1?aintenance interrupt active.
data sheet january 1998 t7256 single-chip nt1 (scnt1) transceiver lucent technologies inc. 39 microprocessor interface description (continued) timing the microprocessor interface is compatible with any microprocessor that supports a synchronous serial micropro- cessor port such as the following: n nec 1 75402 n motorola 2 mc68hc05 and mc68302 scp port n intel 3 80c51 5-2300 (c) figure 12. nec and motorola microprocessor port connections the synchronous interface consists of the microprocessor input clock (sck), serial data input (sdi), and serial data output (sdo). a microprocessor interrupt lead (int ) is also included. these connections are shown in figure 12 for applications using either nec or motorola microprocessors. figure 13 shows the connections for applica- tions using a multiplexed data out/in scheme such as the intel 80c51 or equivalent. 5-2301 (c) figure 13. intel microprocessor port connections 1. nec is a registered trademark of nec electronics, inc. 2. motorola is a registered trademark of motorola, inc. 3. intel is a registered trademark of intel corporation. nec or motorola microprocessor interrupt in clock out data i n data out t7256 sck sdo sdi 11 15 14 12 int intel 80c51 or equivalent microprocessor interrupt in clock out data out/in t7256 sck sdo sdi 11 15 14 12 int
data sheet t7256 single-chip nt1 (scnt1) transceiver january 1998 40 lucent technologies inc. microprocessor interface description (continued) timing (continued) note: if sclk is initially low, it must be held high for >300 m s before its first falling edge. from that point forward, the above timing applies. 5-2302 (c) figure 14. synchronous microprocessor port interface format sclk sdi sdo 12 34 567 8 ca7 ca6 ca5 ca4 ca3 ca2 ca1 ca0 command msb lsb msb lsb shift in sample shift in 1234 5678 di7 di6 di5 di4 di3 di2 di0 di1 do7 do6 do5 do4 do3 do2 do0 do1 don't care 300 ? 1 ca7 3 10 ? 3 10 ? address data shift out figure 14 shows the basic transfer format. all data transfers are initiated by the microprocessor, although the interrupt may indicate to the microprocessor that a register read or write is required. the microprocessor should normally hold the sck pin high during inactive periods and only make transitions during register trans- fers. the maximum clock rate of sck is 960 khz. data changes on the falling edge of sck and is latched on the rising edge of sck. each complete serial transfer consists of 2 bytes (8 bits/byte). the ?st byte of data received over the sdi pin from the microprocessor consists of command/address information that includes a 5-bit reg- ister address in the least signi?ant bit positions (ca4?a0) and a 3-bit command ?ld in the most sig- ni?ant bit positions (ca7?a5). the byte is de?ed as follows: n bits ca7?a5: 001 = read, 010 = write, all other bit patterns will be ignored. n bits ca4?a0: 00000 = register address 0, 00001 = register address 1, etc. the second byte of data received over the sdi pin con- sists of write data for ca7?a5 = 010 (write) or don't care information for ca7?a5 = 001 (read). the data transmitted over the sdo pin to the micropro- cessor during the first byte transfer is a don't care for both read and write operations. the second byte trans- mitted over the sdo pin consists of read data for ca7 ca5 = 001 (read) or don't care information for ca7 ca5 = 010 (write). in order for the t7256 to recognize the identity (com- mand/address or data) of the byte being received, it is required that the time allowed to transfer an entire instruction (time from the receipt of the ?st bit of the command/address byte to the last bit of the data byte) be limited to less than 300 m s. this limits the minimum sck rate to 60 khz. if the complete instruction is received in less than 300 m s, the t7256 accepts the instruction immediately and is ready to receive the next instruction after a 10 m s delay. if the complete instruc- tion is not received within 300 m s, the bits received in the previous 300 m s are discarded and the interface is prepared to receive a new instruction after a 10 m s delay. in addition, a minimum 10 m s delay must exist between the command/address and data bytes.
data sheet january 1998 t7256 single-chip nt1 (scnt1) transceiver lucent technologies inc. 41 microprocessor interface description (continued) timing (continued) for microprocessors using a multiplexed data out/in pin to drive sdi and sdo (as shown in figure 13), a read instruction to t7256 will require that the microproces- sor data in/out pin be an output during the command/ address byte written to t7256, and then switch to an input to read the data byte t7256 presents on the sdo pin in response to the read command. in this case, the microprocessor data in/out pin must 3-state within 1.46 m s of the ?al sck rising edge of the command/ address byte to ensure that there is no contention between the microprocessor data out pin and the t7256 sdo pin. time-division multiplexed (tdm) bus description the tdm bus facilitates b1-, b2-, and d-channel com- munication between the t7256 and peripheral devices such as codecs, hdlc processors, time-slot inter- changers, synchronous data interfaces, etc. the follow- ing list is a subset of the devices that can connect directly to the t7256 tdm bus: n lucent t7570 and t7513 codecs n lucent t7270 time-slot interchanger n lucent t7121 hdlc formatter n national semiconductor*3070 codec the bus can be used to extract data from s/t- or u-interface receivers, process the data externally, and source data to the appropriate transmitters with the processed data. the bus can also be used to simply monitor 2b+d channel data ?w within the t7256 with- out modifying it. the bus also supports board-level test- ing procedures using in-circuit techniques (see the board-level testing section for more details). upon powerup, the tdm bus is not selected. pins 4, 7, 8, and 9 form the tdm bus when tdmen is set to 0 (register gr2, bit 5). the tdm bus consists of a 2.048 mhz output clock (tdmclk), data in (tdmdi), data out (tdmdo), and a programmable frame strobe lead (fs). the frame * national semiconductor is a registered trademark of national semiconductor corporation. strobe timing can be con?ured via the microprocessor register bits fsc and fsp in register tdr0. data appearing and expected on the bus is controlled via the b1-, b2-, and d-channel data ?w register bits (regis- ters dfr0 and dfr1). the tdmclk and fs outputs only become active if one or more of the tdm time slots is enabled (see register dfr1, table 8). clock and data format the clock and data signals for the tdm bus are tdmclk, tdmdo, and tdmdi (see figure 15). tdmclk is a 2.048 mhz output clock. tdmdo is the 2b+d data output for data derived from either the s/t-interface receiver, u-interface receiver, or both. the tdmdo output driver is only active during a time slot when it is driving data off-chip; otherwise, the output driver is 3-stated (this includes the 6-bit interval in the d-channel octet). tdmdi is the 2b+d data input for data used to drive either the s/t-interface transmitter, u-interface transmitter, or both. on both the tdmdo and tdmdi leads, six 8-bit time slots are reserved for the b1-, b2-, and d-channels associated with the s/t- and u-interfaces. the relative locations of the time slots are ?ed; however, the frame strobe is programmable. the total number of time slots available within each frame strobe period is 32. during unused time slots, data on tdmdi is ignored and tdmdo is 3-stated. frame strobe the fs frame strobe is a programmable output associ- ated with the tdm bus. fs can be con?ured to serve as an envelope strobe for any of the six reserved time slots available on the bus: u-interface b1, b2, and d and s/t-interface b1, b2, and d. fs can also be pro- grammed as a 2b+d envelope for either the u-interface or s/t-interface time slots. fs can be used to directly drive a codec for voice applications or can be used to control other external devices such as hdlc control- lers. figure 15 shows the relationship between the tdmclk, tdmdo, and tdmdi time slots, and the fs strobe for some example programmable settings. detailed descriptions of tdm bus interface timing are given in the timing characteristics section of this docu- ment.
data sheet t7256 single-chip nt1 (scnt1) transceiver january 1998 42 lucent technologies inc. time-division multiplexed (tdm) bus description (continued) frame strobe (continued) 5-2303 (c) figure 15. tdm bus time-slot format 8-bit time slot u-intfc b1 u-intfc b2 u-intfc d s/t-intfc b1 s/t-intfc b2 s/t-intfc d b11 b12 b13 b14 b15 b16 b17 b18 b21 b22 b23 b24 b25 b26 b27 b28 d1 d2 tdmdo/ tdmdi tdmclk b1 example fsc = 110 and fsp = 1 2b+d example fsc = 001 and fsp = 1 fs fs b11 b12 b13 b14 b15 b16 b17 b18 b21 b22 b23 b24 b25 b26 b27 b28 d1 d2
data sheet january 1998 t7256 single-chip nt1 (scnt1) transceiver lucent technologies inc. 43 data flow matrix description b1-, b2-, d-channel routing the t7256 supports extremely flexible b1-, b2-, and d- channel routing among major circuit blocks in order to accommodate various applications. channel routing is controlled via the data flow control registers, dfr0 and dfr1. figure 16 shows a block diagram of the device and the channel paths to and from the u transceiver, s/t transceiver, and tdm bus interface. channel flow is determined by specifying the source of channel data at the three points shown in the figure: (1) u transceiver transmit input, (2) s/t transceiver transmit input, and (3) tdm bus transmit input. channel flow at the tdm bus receive input (4) is determined, by default, from the set- tings at the other three points. a switch matrix within the data flow matrix block routes channels to and from the specified points. as an example, below are the register settings required to con?ure the device as an nt1, with the b1 and b2 channels in both the u- to s/t- and s/t- to u-interface directions made available on the tdm bus for monitor- ing: n tdmen = 0 (enables tdm bus). n uxb1 = 11, uxb2 = 11, uxd = 1 (routes s/t-inter- face receive channels to u-interface transmitter). n sxb1 = 11, sxb2 = 11, sxd = 1 (routes u-interface receive channels to s/t-interface transmitter). n tdmb1s = tdmb2s = 0 (brings out b1 and b2 channels in s/t- to u-interface direction to tdm bus). n tdmds = 1 (d channel in s/t- to u-interface direc- tion not brought out on tdm bus). n tdmb1u = tdmb2u = 0 (brings out b1 and b2 channels in u- to s/t-interface direction to tdm bus). n tdmdu = 1 (d channel in u- to s/t-interface direc- tion not brought out on tdm bus). refer to the board-level testing section for another example of using the data ?w matrix to route data. 5-2304 (c) figure 16. b1-, b2-, d-channel routing tdm bus intfc. ? interface ? interface data flow controller switch matrix tdm bus interface transmit receive transmit u transceiver s/t transceiver 2 receive 3 1 4
data sheet t7256 single-chip nt1 (scnt1) transceiver january 1998 44 lucent technologies inc. loopbacks the ?ure below shows the layer-1 loopbacks that are de?ed in itu-t i.430, appendix i and ansi speci?a- tion t1.605, appendix g. a complete discussion of these loopbacks is presented in itu-t i.430, appendix i. the t7256 supports loopbacks 2, c, and u. loop- back u is not de?ed in the standards, but is provided by the t7256 via register gr1, bit 0. loopback 2 is the eoc 2b+d loopback de?ed in the standards. individual b-channel eoc loopbacks are looped upstream of the data ?w matrix. loopback c is sup- ported via the dfr0 register, bits 4?. in a loopback 2, the 2b+d data is looped as close to the s/t-interface as possible (just short of the s/t-inter- face device pins). during this loopback, the device overrides the sxe bit to force all 0s in the echo channel and also overrides the sxb1, sxb2, sxd, uxb1, uxb2, and uxd data ?w matrix bits to force a u- to s/t-interface data path. note that the actual register bits themselves are unaffected. if autoeoc = 0, (reg- ister gro, bit 4), these registers must be set up manu- ally. 5-2482 (c) figure 17. location of the loopback con?urations (reference itu-t i.430 appendix i) loopbac k channel(s) looped te1 = isdn terminal r = r reference point 2 2b+d channels te2 = non-isdn terminal s = s reference point 3 2b+d channels ta = terminal adapter t = t reference point 4 b1, b2 nt2 = network termination 2 u = u reference point c b1, b2 nt1 = network termination 1 b1 or b2 2b+d, b1, b2 lt = line termination a 2b+d, b1, b2 te1 s nt2 nt1 tu lt 2c u b1 3 b2 ta te2 r 4 s 4 a a
data sheet january 1998 t7256 single-chip nt1 (scnt1) transceiver lucent technologies inc. 45 modes of operation to provide ?xibility in the system architecture, the t7256 transceiver can operate in stand-alone mode (no micro- processor) to provide basic nt1 functionality or it can operate under microprocessor control through the serial interface to provide enhanced nt1 operation. in stand-alone mode, the t7256 automatically handles u- and s/t-interface activation, control, and maintenance according to the ansi t1.601 and itu-t i.430/ansi t1.605 standards. the device is con?ured for this mode via internal pull-ups and pull-downs and microprocessor register default values during an external reset . table 26 shows the transceiver control pins that may be relevant in stand- alone mode. table 26. stand-alone mode in microprocessor mode, the t7256 supports all the features of stand-alone mode, plus allows enhanced control including s/q-channel support, tdm highway access, and manual eoc and u overhead bit manipulation. the microprocessor port can be accessed at any time via the sdi, sdo, and sck pins (see microprocessor interface description and timing characteristics sections for details). table 27 shows the transceiver control pins that may be relevant in microprocessor mode, or whose operation may change based on register settings. table 27. microprocessor mode pin symbol function 2 optoin maintenance pulse streams are decoded and automatically implemented us- ing the ansi state machine requirements. 4 syn8k/lbind/fs performs the syn8k or lbind depending on the state of syn8k_ctl/sdi (pin 12) during an external reset . 7 fte/tdmi performs the fte function. selects the s/t-interface timing recovery mode. 8 ps2e/tdmdo performs the ps2e function. controls the ps2 bit in the transmit u-interface data stream. 9 ps1e/tdmclk performs the ps1e function. controls the ps1 bit in the transmit u-interface data stream. 11 actmode/int performs the actmode function. controls the act bit in the transmit u-interface data stream during 2b+d loopbacks. 12 syn8k_ctl/sdi held high or low on powerup or reset to control syn8k/lbind/fs (pin 4). 15 autoact/sck held high or low on powerup or reset to control automatic activation attempt. 43 reset resets the device. the states of sck, sdi, and int are read upon exiting reset state. pin symbol comment 2 optoin controlled by microprocessor bit autoctl (register gr0). 4 syn8k/lbind/fs controlled by microprocessor bit tdmen (register gr2). 6 iloss controlled by microprocessor bit autoctl (register gr0). 7 fte/tdmdi controlled by microprocessor bit tdmen (register gr2). 8 ps2e/tdmdo controlled by microprocessor bit tdmen (register gr2). 9 ps1e/tdmclk controlled by microprocessor bit tdmen (register gr2). 11 actmode/int interrupt output for the microprocessor interface. 12 syn8k_ctl/sdi serial data input for the microprocessor interface. 14 sdo serial data output for the microprocessor interface. 15 autoact/sck master clock input for the microprocessor interface.
data sheet t7256 single-chip nt1 (scnt1) transceiver january 1998 46 lucent technologies inc. stled description the stled pin is used to drive an led and provides a visual indication of the current state of the t7256. the stled control is typically con?ured to illuminate the led when stled is low. this convention will be assumed throughout this section. table 28 describes the four states of stled, the list of system conditions that produce the state, and the cor- responding ansi states, as de?ed in ansi t1.601- 1992 (tables c1 and c4) and etsi etr 080-1992 (tables a3 and i2). note: the etsi state names begin with the letters nt instead of h. also, the etsi state tables do not include a state nt11 because it is con- sidered identical to state nt6. table a3 of the etsi standard contains the additional states nt6a, nt7a, and nt8a to describe states related to the eoc loopback 2 (2b+d loop- back). the most likely ansi state for each stled state is shown in bold typeface below. the ?w chart in figure 18 illustrates the priority of the logic signals which control the stled pin. in the deci- sion diamonds, those names in all capital letters denote t7256 register bit names. the reset, autoctl, autoeoc, and stoa are r/w bits con- trolled by the user via the microprocessor interface. the xact, oof, and aib bits are read-only bits deter- mined by the internal logic based on system events and can be monitored by the user via the microproces- sor interface. other names in the decision diamonds (quiet mode, iloss mode, loop2, info 2, info 4) represent system conditions that cannot be directly monitored or controlled by the microprocessor inter- face. table 28. stled states * these are etsi dtr/tm-3002 states not yet de?ed in ansi t1.601, although they are de?ed in revised ansi tables which are currently on the living list (i.e., not yet an of?ial part of the standards document). ? state h8(a) is most likely when u-interface bit uoa = 0. stled state list of system conditions that can cause stled state corresponding ansi states high (led off) reset (pin 43) = 0 autoctl = 0 (register gr0, bit 3), or autoeoc = 0 (register gr0, bit 4), or stoa = 0 (register gr2, bit 7) na u and s/t not active h0, h1 , h10, h12 8 hz flashing reset = 0 (register gr0, bit 0) quiet mode active, or iloss mode active na u activation attempt in progress h2, h3, h4 aib = 0 (register cfr1, bit 6) h7, h8 eoc-initiated 2b+d loopback active nt6a*, nt7a*, nt8a * 1 hz flashing u active, s/t not fully active h6, h6(a), h7 , h11, h8(a) ? , h8(b), h8(c) low (led on) u and s/t fully active h8
data sheet january 1998 t7256 single-chip nt1 (scnt1) transceiver lucent technologies inc. 47 stled description (continued) 5-3599d (c) figure 18. stled control flow diagram reset pin low? stled = off autoctl = 0 autoeoc = 0, or stoa = 0 reset = 0, quiet mode = active, or iloss mode = active aib = 0 info2 = 0? info4 = 0? stled = 1 hz stled = off stled = 8 hz stled = off stled = 8 hz stled = 8 hz stled = 1 hz stled = on stled = 8 hz yes no yes no yes no yes yes no no no yes ye s ye s ye s no no no start xact = 0? oof = 0? loop2 = active?
data sheet t7256 single-chip nt1 (scnt1) transceiver january 1998 48 lucent technologies inc. eoc state machine description the following list shows the eight eoc states de?ed in ansi t1.601 and etsi etr 080. the bit pattern below represents the state of u-interface overhead bits eoci1?oci8, respectively (see table 2). 01010000?perate 2b+d loopback. 01010001?perate b1 channel loopback. 01010010?perate b2 channel loopback. 01010011?equest corrupt crc. 01010100?otify of corrupted crc. 11111111?eturn to normal (default). 00000000?old state. 10101010?nable to comply. normally, the t7256 automatically handles the eoc channel processing per the ansi and etsi standards. there may be some applications where manual control of the eoc channel is desired (e.g., equipment that is meant to test the eoc processing of upstream elements by writing incorrect or delayed eoc data). this can be accomplished by setting autoeoc = 0 (register gr0, bit 4). the eoc state change interrupt is enabled by set- ting eocscm = 0 (register uir1, bit 0). this allows state changes in the received eoc messages (registers ecr2 and ecr3) to be indicated to the microproces- sor by the assertion of uint = 1 (register gir0, bit 0) and eocsc = 1 (register uir0, bit 0). the micropro- cessor reads registers ecr2 and ecr3 to determine which received eoc bits changed. then, it updates the transmit eoc values by writing registers ecr0 and ecr1 and takes appropriate action (e.g., enable a requested loopback). the total manual eoc procedure consists of the following steps: 1. microprocessor detects int pin going low. 2. microprocessor reads gir0 and determines that the uint bit is set. 3. microprocessor reads uir0 and determines that the eocsc bit is set. 4. microprocessor reads ecr2. 5. microprocessor reads ecr3. 6. microprocessor interprets newly received eoc mes- sage and determines the appropriate response. 7. microprocessor writes ecr0 based on results of step 6. 8. microprocessor writes ecr1 based on results of step 6. the maximum time allowed from the assertion of the int pin (step 1) until the completion of the last write cycle to the eoc registers (step 8) is 1.5 ms. ansi maintenance control description the ansi maintenance controller of the t7256 can operate in fully automatic or in fully manual mode. automatic mode can be used in applications where autonomous control of the metallic loop termination (mlt) maintenance is desired. the mlt capability implemented with the lucent lh1465ab and an opto- coupler provides a dc signature, sealing current sink, and maintenance pulse-level translation for the testing facilities. maintenance pulses from the u-interface mlt circuit are received by the optoin pin and digitally ?- tered for 20 ms. the device decodes these pulses according to ansi maintenance state machine require- ments and responds to each request automatically. for example, the t7256 will place itself in the quiet mode if six pulses are received from the mlt circuitry. microprocessor interrupts in register mir0 are avail- able for tracking maintenance events if desired. manual mode can be used in applications where an external maintenance decoder is used to drive the reset and iloss pins of the t7256. in this mode, the reset pin places the device in quiet mode and the iloss pin controls sn1 tone transmission. maintenance events are not available in register mir0 when in manual mode.
data sheet january 1998 t7256 single-chip nt1 (scnt1) transceiver lucent technologies inc. 49 s/t-interface multiframing controller description if an external microprocessor is available, the t7256 can provide the capability of supporting multiframing as de?ed in itu-t i.430 section 6.3.3 and ansi t1.605 section 7.3.3. multiframing provides layer-1 signaling capability between the tes and the nt in both direc- tions through the use of extra channels referred to as the s channel for the nt-to-te direction and the q channel for the te-to-nt direction (see figure 8 in this data sheet for the location of the s and q bits in the nt and te frames). this signaling capability is similar to the eoc channel between the lt and nt on the u-inter- face. the s and q channels exist only between the te and nt, and there is no requirement that the nt trans- fers this information to the u-interface. the requirement for multiframing capability is treated somewhat differently in ansi t1.605, itu-t i.430, and etsi ets 300 012. the ansi standard states that the use of the s- and q-channels is optional (section 7.3.3). nts that do not support these channels are not required to encode the fa and m bits as required for multiframing. tes that do not support these channels still must provide for identi?ation of the q-bit positions and, if identi?d, must set each q bit to a binary one. ansi de?es a set of q-channel messages, and divides the s channel into ?e subchannels, de?ing messages for s subchannels 1 and 2 (see t1.605 tables 8 and 9). itu-t i.430 contains similar requirements for the s and q channels as t1.605, with the following exceptions: 1. there is no "far-end code violation" message for s subchannel 1 (see itu-t i.430, table 9). 2. s subchannel 2 is not de?ed. etsi ets 300 012 deviates slightly from itu-t i.430. it states that the nt1 will not provide multiframing, and therefore the fa bit from nt-to-te must be set to zero (table a.1, subclause a.6.3.3). an nt2, however, may optionally provide multiframing in accordance with itu- t i.430. in either case, the tes must provide for identi? cation of the q-bit positions. the multiframing mechanism in the t7256 is controlled by the microprocessor. normally, multiframing is dis- abled (the nt transmits all zeros in the fa and m bit positions and all ones in the s bit positions). to enable multiframing, set multif = 0 in bit 5 of register gr0. note that multiframing should only be enabled after the te interface is fully active (i.e., transmitting info3). in order to guarantee this, the controller should implement the following procedure: 1. initialize multif = 1 (this is the default on pow- erup). 2. monitor actr (register cfr1, bit 0) with the micro- processor to detect when the system has activated and has received info3. actr re?cts the state of the u-interface act bit from the lt, and is sent by the lt in response to a reception of the act bit from the nt. the nt sets act = 1 only after receiving info3 on the s/t-interface; so waiting for actr = 1 ensures that info3 is being received. the monitoring of the actr bit can be interrupt- driven using the actsc bit in interrupt register uir0. 3. when actr = 1 is detected, set multif = 0 to enable multiframing. 4. monitor for a change from xact = 1 to xact = 0. this can also be interrupt-driven using the actsc bit in interrupt register uir0. 5. when xact = 0 is detected, this indicates that the system has deactivated. at this point, go back to step #1 and repeat the proce- dure.
data sheet t7256 single-chip nt1 (scnt1) transceiver january 1998 50 lucent technologies inc. s/t-interface multiframing controller description (continued) once multiframing has been enabled, the microproces- sor can read the q-channel data that is received and control the s subchannel data that is transmitted via registers mcr0?cr5. the reception of a new q- channel message is indicated to the microprocessor when interrupt bit qsc = 1 (q-bits state change bit, register sir0 bit 1). the microprocessor is informed that a new s-subchannel message may be transmitted when interrupt bit som = 1 (start of multiframe bit, reg- ister sir0, bit 0). to enable the som and qsc inter- rupts, set somm = 0 and qscm = 0 (register sir1, bits 0 and 1). when an interrupt occurs, the global interrupt bits (register gir0) can be read by the micro- processor to determine the source of the interrupt (reg- ister uint, sint, or mint). an interrupt asserted in the sir0 register is indicated by sint = 1. reading the sir0 interrupt register clears the som and qsc inter- rupt bits in preparation for the next occurrence. it should be noted that the som interrupt is asserted 27 m s after the start of a multiframe and the s-subchan- nel bits are latched in the mcr1?cr5 registers 3 m s prior to the start of the next multiframe. since 30 m s (27 m s + 3 m s) of time is used by the device, the microprocessor has 4.97 ms of a total 5 ms multiframe to load the next value of s-subchannel bits. the q- channel bits in the mcr0 register are updated every multiframe at the same time that som is asserted. changes in any of the q bits are indicated to the micro- processor by qsc = 1. board-level testing the t7256 provides several board-level testability fea- tures. for example, the highz pin 3-states all digital outputs for bed-of-nails testing. also, various loopbacks can be used to verify device functionality. stimulus/response testing data transparency of the b1, b2, and d channels can be veri?d by the combined use of the tdm bus and microprocessor port. data ?w within the device can be con?ured by the external controller through the micro- processor port, and b1-, b2-, and d-channel data can be transmitted into and received from the device via the tdm bus. using this method, arbitrary data patterns can be used to stimulate the device and combinations of loopbacks can be exercised to help detect and iso- late faults. figure 19 illustrates this general-purpose testing con?uration. tdmdi data can be routed through the device and back to tdmdo at both the u- or s/t-interfaces. for looping at u-interface, the procedure is as follows: n disconnect the u-interface from the telephone net- work. n set tdmen = 0 in register gr2, bit 5. n set register dfr0 to 11110101. n set register dfr1 to 00011110. n set register tdr0 as required for the desired frame strobe location and polarity. now, write lpbk in register gr1 to a 0. this causes the chip to enter the u-interface loopback mode. any data entering the tdm highway on tdmdi will be looped back (with some delay) on tdmdo. for looping of the s/t-interface, the procedure is as fol- lows: n set tdmen = 0 in register gr2, bit 5. n set register dfr0 to 01011111. n set register dfr1 to 11100001. n set register tdr0 as required for the desired frame strobe location and polarity. n set afrst = 0 (register cfr0, bit 1) and stoa = 0 (register gr2, bit 7). this causes the s/t-interface to force activation while keeping the u-interface inac- tive. now, externally short the transmit pins to the receive pins on the s/t-interface (e.g., in figure 21, short j2? to j2? and short j2? to j2?). this causes a loopback of the s/t-interface that results in tdmdi data being looped to tdmdo.
data sheet january 1998 t7256 single-chip nt1 (scnt1) transceiver lucent technologies inc. 51 s/t-interface multiframing controller description (continued) stimulus/response testing (continued) 5-2305 (c) figure 19. external stimulus/response con?uration ? interface implements data path transmit transmit u transceiver receive receive s/t transceiver rnr rpr tpr tnr s/t-interface shorted u-interface open circuited data stimulus & received data compare external test machine data flow register programming external controller data flow controller tdm bus interface tdmdo tdmdi
data sheet t7256 single-chip nt1 (scnt1) transceiver january 1998 52 lucent technologies inc. application briefs t7256 reference circuit a reference circuit illustrating the t7256 in a stand- alone nt1 application is shown in figures 20 and 21. this depicts a complete stand-alone nt1 design with the exception of power supply circuitry and power sta- tus monitoring circuitry. a bill of materials for the sche- matic is shown in table 29. note that speci? applications may vary depending on individual require- ments. u-interface the u-interface attaches to the board at rj-45 connec- tor j1 (see figure 20). f1 and vr2 provide overcurrent and overvoltage protection, respectively. these two devices in combination with transformer t1 provide protection levels required by fcc part 68 and ul* 1459. for an in-depth discussion of protection issues, the following application notes are helpful. 1. ?vervoltage protection of solid-state subscriber loop circuits, lucent analog line card components data book (ca94-007alc) 800-372-2447. 2. protection of telecommunications customer premesis equipment, raychem ? corporation, 415-361-6900. c16 is a 1.0 m f dc blocking capacitor that is required per ansi t1.601, section 7.5.2.3. the 250 v rating of c16 is governed by the maximum breakdown voltage of vr2, since the capacitor must not break down before vr2. the resistance of r13 (21 w ) and f1 (12 w ) pro- vides a total line-side resistance of 33 w , which is required when using the lucent 2754h2 transformer (see the note at the end of table 29 for information on r13 values when using other transformers). on the device side of the u-interface transformer, vr1 provides secondary overvoltage protection of 6.8 v. optional capacitors c13 and c14 provide common- mode noise suppression for applications that are required to operate in the presence of high common- mode noise. r6 and r7 provide the necessary external hybrid resistors. * ul is a registered trademark of underwriters laboratories, inc. ? raychem is a registered trademark of raychem corporation. s/t-interface the s/t-interface attaches to the board at rj-45 con- nector j2 (see figure 21). l1 is a high-frequency com- mon-mode choke used to minimize emi. r24 and r25 are 100 w terminations required by itu i.430 section 8.4. jumper-selectable resistors r26 and r27 provide for a 50 w termination option instead of the standard 100 w termination. this is useful in con?urations where none of the tes have terminating resistors. dual-transformer t2 has a standard footprint that can accept isdn transformers from several vendors. on the device side of the s/t-interface transformer, d2 d11 and vr3? provide overvoltage protection for the device pins. r20?3 provide current limiting for cases where one or more of the protection diodes conducts due to an overvoltage condition. capacitor c17 pro- vides suppression of common-mode noise that might otherwise be introduced onto the receiver input pins, effectively increasing the receiver's cmrr. note that the s/t transformer must have a center tap on the device side in order to use this scheme. r16 and r17 in combination with r20 and r21, respectively, provide the 121 w of resistance required by the t7256 on each transmitter output pin. r18 and r19 are the 10 k w , 10% resistors required on the receiver input pins. mlt circuit the metallic loop termination (mlt) circuit (u3 and related components in figure 20) provides a dc termi- nation for the loop per ansi t1.601, section 7.5. r14 and r15 are power resistors used to sink current dur- ing overvoltage fault conditions. the optoisolater (u2) provides signal isolation and voltage translation of the signaling pulses used for nt maintenance modes, per t1.601, section 6.5. the t7256 interprets these pulses via an internal ansi maintenance state machine, and responds accordingly. for applications outside north america, the mlt circuit is not required. status led d1 in figure 20 is an led that is controlled by the stled pin of the t7256 and indicates the status of the device (activating, out-of-sync, etc.). table 28 and fig- ure 18 of this data sheet details the possible states of the stled pin and the meaning of each state.
data sheet january 1998 t7256 single-chip nt1 (scnt1) transceiver lucent technologies inc. 53 application briefs (continued) t7256 reference circuit (continued) power status leads ansi t1.601 section 8.2.4 de?es u-interface nt power status bits ps1 and ps2. these bits are transmit- ted across the u-interface via the u maintenance chan- nel. on the t7256, these bits are controlled by pins 8 and 9 (ps2e and ps1e). when the tdm highway is used (nt1+ or ta modes), the ps1/ps2 bits are con- trolled by internal registers that are written by an exter- nal microprocessor. an nt1 typically has circuitry that monitors the status of the power supply and sets ps1 and ps2 accordingly. in general, power status monitor- ing circuitry is dependent on various system parame- ters and requirements, and must be designed based on the speci? applications requirements. for this reason, there is no power status monitoring circuitry shown in this design. instead, pull-ups r1 and r2 in figure 20 are provided to force a default indication of primary and secondary power good status. fixed/adaptive timing control as detailed in table 1, pin 7 of the t7256 controls whether the s/t-interface will use ?ed or adaptive tim- ing recovery. when there is no connection to pin 7, an internal 100k pull-up holds the pin high, which causes the chip to default to adaptive timing recovery. jmp1 is provided (see figure 20) to change the timing recovery mode to ?ed timing by pulling pin 7 down through a 5.1 k w resistor.
data sheet t7256 single-chip nt1 (scnt1) transceiver january 1998 54 lucent technologies inc. application briefs (continued) t7256 reference circuit (continued) 5-4048(c).d figure 20. t7256 stand-alone reference circuit-a c3 0.01 ? +5 v c1 0.01 ? +5 v +5 v a c11 0.01 ? 7 8 9 10 11 12 13 14 15 16 17 fte/tdmdi ps2e/tdmdo ps1e/tdmclk gndd int sdi v ddd sdo sck gnd d ckout +5 v r1 5.1 k w connect ps1e and ps2e to power status monitoring circuit if present c2 0.01 ? +5 v +5 v status led d1 r4 825 w v ddo x1 x2 v dda tnr tpr rnr rpr vrcm 6 5 4 3 2 1 44 43 42 41 40 iloss highz reset +5 v 18 19 20 21 22 23 24 25 26 27 28 +5 v a x1 15.360 mhz c6 0.1 ? rpr rnr tpr tnr c8 0.1 ? c12 0.1 ? 39 38 37 36 35 34 33 32 31 30 29 v dda sdinp sdinn hp lon gnd a v dda lop hn vrn vrp r6 16.9 w r7 16.9 w c10 0.01 ? +5 v a sa6.0ca 1 5 7 9 10 6 c16 1.0 ? c13 3300 pf c14 3300 pf r13 21 w vr2 f1 tr600-150 u-interface circuit c7 0.01 ? +5 v a u1 t7256 r5 5.1 k w c5 1.0 ? vr1 t1 1:1.5 2754h2 r14 1.1 k w 2 w pr+ t r pr u3 lh1465ab 1 2 3 4 tc rs pd com 8 7 6 5 r12 137 w c15 0.1 ? r10 10 k w r8 17.8 k w +5 v r9 2.2 m w 5 6 8 2 3 u2 hcpl-0701 mlt circuit 7 for north american applications only 2 1 3 5 7 8 6 4 j1 rj-45 r2 5.1 k w r3 5.1 k w 1 2 jmp1 por circuit c9 820 pf r15 1.1 k w 2 w r11 137 w ground/power planes should not come within 2.5 mm of the circuitry within this dashed area note: the width of these tracks should be 50 mils gnd o stled v dda v ddd gnd a gnd d syn8k gnd a gnd a (place this capacitor as close as possible to the lh1465) smp100-140 optoin c4 0.01 ?
data sheet january 1998 t7256 single-chip nt1 (scnt1) transceiver lucent technologies inc. 55 application briefs (continued) t7256 reference circuit (continued) 5-4047(f).a note: see question/answer section, #35. figure 21. t7256 stand-alone reference circuit-b d4 d5 d8 d9 d6 d7 d10 d11 d2 d3 vr3 vr4 tpr r16 r20 r17 r21 r18 r22 r19 r23 tnr 16 15 14 13 1 2 3 4 t2 r24 100 w r26 100 w jmp2 4 3 2 1 5 6 7 8 l1 pe65554 2 1 3 5 7 8 6 4 j2 rj-45 rpr rnr 12 11 10 9 5 6 7 8 r25 100 w r27 100 w jmp3 75 w 46.4 w 75 w 46.4 w 10 k w 46.4 w 10 k w 46.4 w pe65498 s/t-interface circuit c17 0.1 m f 2.5:1 1 2 1 2
data sheet t7256 single-chip nt1 (scnt1) transceiver january 1998 56 lucent technologies inc. application briefs (continued) t7256 reference circuit (continued) table 29. t7256 reference schematic parts list 1. kemet is a registered trademark of kemet laboratories company, inc. 2. philips is a registered trademark of philips manufacturing company. 3. vitramon is a registered trademark of vitramon, inc. 4. hewlett packard is a registered trademark of hewlett-packard company. 5. polyswitch is a registered trademark of raychem corporation. 6. bel and bel fuse are registered trademarks of bel fuse, inc. 7. molex is a registered trademark of molex, inc. 8. pulse engineering is a registered trademark of pulse engineering, inc. 9. dale is a registered trademark of dale electronics, inc. reference designator description source part # c[1?, 7, 10, 11] ceramic chip capacitor, 0.01 m f, 10%, 50 v, x7r kemet 1 c1206c103k5rac c5 tantalum chip capacitor, 1.0 m f, 10%, 16 v kemet t491a105k016as c[6, 8, 12, 17] ceramic chip capacitor, 0.1 m f, 10%, 50 v, x7r kemet c1206c104k5rac c9 ceramic chip capacitor, 820 pf, 5%, 50 v, npo kemet c0805c821j5gac c[13, 14] ceramic chip capacitor, 3300 pf, 10%, 50 v, x7r kemet c1206c332f5rac c15 polyester capacitor, 0.1 m f, 63 v, 10% note: insulation resistance of this part must be >2 g w . philips 2 2222 370 12104 c16 capacitor, 1.0 m f, 250 v, 10% alternate: philips 2222 373 41105 vitramon 3 , via tmi (rep) (215) 830-8500 vj9253y105kxpm d1 green surface-mount led hewlett packard 4 hsmg-c650 d[2?1] smt switching diode philips pmll4151 f1 overcurrent protector (polyswitch 5 ) alternate: bel fuse 6 mjs 1.00a, (201) 432-0463 see note at the end of this table. raychem (415) 361-6900 tr600-150 j1, j2 rj-45 8-pin modular jack (standard height) molex 7 15-43-8588 jmp1? two-position header with shorting jumper multiple l1 high-frequency common-mode choke alternate: pulse pe-65854 (surface mount) pulse engineering 8 (619) 674-8100 pe65554 r[1?, 5] smc resistor, 5.1 k w , 1/8 w, 5% dale 9 crcw1206512j r4 smc resistor, 825 k w , 1/8 w, 1% dale crcw12068250f r6, 7 smc resistor, 16.9 k w , 1/8 w, 1% dale crcw120616r9f r8 smc resistor, 17.8 k w , 1/8 w, 1% dale crcw12061783f r9 smc resistor, 2.2 m w , 1/8 w, 5% dale crcw1206225j r[10, 18, 19] smc resistor, 10 k w , 1/8 w, 5% dale crcw1206103j [r11, 12] smc resistor, 137 w , 1/8 w, 1% dale crcw12061370f r13 smc resistor, 21.0 w , 1 w, 1% dale wsc-1
data sheet january 1998 t7256 single-chip nt1 (scnt1) transceiver lucent technologies inc. 57 application briefs (continued) t7256 reference circuit (continued) table 29. t7256 reference schematic parts list (continued) 1. kemet is a registered trademark of kemet laboratories company, inc. 2. philips is a registered trademark of philips manufacturing company. 3. vitramon is a registered trademark of vitramon, inc. 4. hewlett packard is a registered trademark of hewlett-packard company. 5. polyswitch is a registered trademark of raychem corporation. 6. bel and bel fuse are registered trademarks of bel fuse, inc. 7. molex is a registered trademark of molex, inc. 8. pulse engineering is a registered trademark of pulse engineering, inc. 9. dale is a registered trademark of dale electronics, inc. 10. valor is a registered trademark of valor electronics, inc. 11. advanced power components is a registered trademark of advanced power technology, inc. 12. vacuumschmelze is a registered trademark of vacuumschmelze gmbh. reference designator description source part # r14, 15 smc resistor, 1.1 k w , 2 w, 5% dale wsc-2 r16, 17 smc resistor, 75 w , 1/8 w, 1% dale crcw120675r0f r20?3 smc resistor, 46.4 w , 1/8 w, 1% dale crcw120646r4f r24?7 smc resistor, 100 w , 1/8 w, 1% dale crcw12061000f t1 isdn u-interface transformer lucent 2754h2 alternates (see footnote at the end of this table.): lucent 2754k2 (1500 vrms breakdown) lucent 2809a (for en60950 compliance) valor 10 pt4084 (619) 537-2500 midcom 671-7759 (605) 886-4385 t2 isdn s-interface dual transformer pulse engineering (619) 674-8100 pe65498 alternates: pulse engineering pe-68988 (single transformer, rein- forced insulation) valor pt5048 (619) 537-2500 (pin compatible) advanced power components 11 , ltd. apc40498 (pin compatible) apc2050s (single transformer, reinforced insulation) us: terry manton, inc. (rep), (201) 447-8821 europe: 44-634-290588 vacuumschmelze 12 (vac) (single transformer, reinforced insulation) t60403-l4097-x017-80 u.s.: (908) 494-3530 europe: 49-6181-38-2026 u1 single-chip nt1 ic, 44-pin plcc lucent t7256 u2 optocoupler hewlett packard hcpl-0701 u3 isdn dc termina- tion ic lucent lh1465ab
data sheet t7256 single-chip nt1 (scnt1) transceiver january 1998 58 lucent technologies inc. application briefs (continued) t7256 reference circuit (continued) table 29. t7256 reference schematic parts list (continued) 1. kemet is a registered trademark of kemet laboratories company, inc. 2. philips is a registered trademark of philips manufacturing company. 3. vitramon is a registered trademark of vitramon, inc. 4. hewlett packard is a registered trademark of hewlett-packard company. 5. polyswitch is a registered trademark of raychem corporation. 6. bel and bel fuse are registered trademarks of bel fuse, inc. 7. molex is a registered trademark of molex, inc. 8. pulse engineering is a registered trademark of pulse engineering, inc. 9. dale is a registered trademark of dale electronics, inc. 10. valor is a registered trademark of valor electronics, inc. 11. advanced power components is a registered trademark of advanced power technology, inc. 12. vacuumschmelze is a registered trademark of vacuumschmelze gmbh. 13. sgs-thomson is a registered trademark of sgs-thomson microelectronics, inc. 14. teccor is a registered trademark of teccor, inc. 15.mtron is a registered trademark of mtron industries, inc., a wholly owned subsidiary of lynch* corporation. * lynch is a registered trademark of lynch corporation. note: the lucent 2754k2 and the valor pt4084 have different winding resistances than the lucent 2754h2, and therefore require a change to the line-side resistor (r15). in addition, if the bel fuse is used in place of the raychem tr600-150 ptc at location f1 (which will sacrifice the resettable protection that the ptc provides), the line-side resistors must be adjusted to compensate for reduced resistance due to the removal of the ptc (12 w ). the following table lists the necessary resistor values for these cases. note that r15 is specified at 1%. this is due to the fact that the values were chosen from standard 1% resistor tables. when a ptc is used, the overall tolerance will be greater than 1%. this is acceptable, as long as the total line-side resistance is kept as close as possible to the ideal value. see question and answer section, #6 for more details. table 30. line-side resistor requirements reference designator description source part # vr1 transient voltage suppressor sgs- thomson 13 sm6t6v8ca alternates: motorola sa6.5ca, p6ke6.8ca, p6ke7.5ca vr2 transient voltage suppressor sgs- thomson smp100-140 alternate: teccor 14 p1602ab (972) 580-7777 vr[3, 4] transient voltage suppressor, 6.8 v motorola 1.5smc6.8at3 alternate: motorola 1n6269a x1 15.36 crystal saronix (415) 856-6900 srx5144 alternates: mtron 15 4044-001 (605) 665-9321 2b elettronica s.d.l. tp0648 39-6-6622432 transformer when raychem tr600-150 is used when bel fuse is used r13 r13 lucent 2754h2 21 w 33.2 w lucent 2754k2 15.4 w 27.4 w lucent 2809a 9.53 21.5 valor pt4084 0 w 10.7 w
data sheet january 1998 t7256 single-chip nt1 (scnt1) transceiver lucent technologies inc. 59 application briefs (continued) using the t7256 in a combination te/ta environment (nt1/ta) the t7256 can be used in applications requiring nt1 and terminal adapter (ta) functionality (nt1/ta). this application brief describes an nt1 that supports con- ventional pots (plain old telephone service) as well as isdn service. a block diagram of this application is shown in figure 22. the microprocessor ( m p) performs the following functions: n runs the isdn call control stack (q.931). n controls the hdlc formatter for performing the lap-d protocol on the d channel. n controls the register con?uration of the t7256. n controls the pots circuitry (i.e., translates signaling such as off-hook into the correct call-control mes- sage, translates dtmf digits from a dtmf receiver, controls the ringer, etc.). n controls access to the b and d channels on the tdm highway for the codecs and hdlc formatter, respec- tively. 5-3646(c).b figure 22. t7256 nt1/ta application block diagram t7256 con?uration when the t7256 is used in the nt1/ta application, the tdm highway must be used in conjunction with the data ?w control registers (dfr0 and dfr1) to control the b- and d-channel data ?w. following is a sug- gested procedure for properly con?uring the t7256 in this application. 1. set tdmen = 0 (register gr2, bit 5) to enable the tdm highway. in this case, the ps1/ps2 functions must be controlled via the microprocessor (register gr1, bits 1 and 2) because pins 8 and 9 are used for tdmdo and tdmclk. note that when the tdm highway is enabled, tdmclk and fs will not become active until at least one of the bits 2? in register dfr1 are enabled (set to 0). 2. the downstream d channel must be monitored by the ta circuit for call-control messages from the switch. this is accomplished via the tdm bus by setting tdmdu = 0 (register dfr1, bit 7). the upstream d channel (which is normally sourced from the s/t-interface) must be sourced by the pots hdlc controller when one of the following events occurs: a. the switch noti?s the pots circuit of an incom- ing call request via a downstream d-channel message. b. a local pots phone goes off-hook (i.e., a call is being placed). in either of these cases, the pots hdlc controller must take control of the d-channel in order to com- plete the call setup for the appropriate pots phone. this is accomplished by setting uxd = 0 (register dfr1, bit 0). 3. the frame strobe pulse envelope and polarity must be con?ured for correct operation with the hdlc controller and codecs using register tdr0. for example, to set an active-high fs pulse that enve- lopes the u-interface b1 channel data (see figure 18), register tdr0 bits 0? should be set to all 1s (default on powerup). this setting can be used with the lucent t7121 hdlc controller because the t7121 can be programmed for any time slot and bit offset from the rising or falling edge of fs. the codecs may require the fs pulse be in a partic- ular position relative to the b-channel data. for example, if two lucent t7513b codecs are used in variable timing mode in this application (one for each pots line), each would require an fs pulse that envelopes the appropriate b-channel data. the con?uration described in the preceding paragraph is adequate for allowing either codec to source or sink b1 channel data to the u-interface, but there is no separate fs pulse available for the b2 channel data. therefore, external glue logic is necessary to generate an fs pulse for the b2 channel data. t7256 u-interface serial interface ? parallel interface hdlc codec, slics, ringers, dtmf receivers, etc. tdm highways s/t-interface
data sheet t7256 single-chip nt1 (scnt1) transceiver january 1998 60 lucent technologies inc. application briefs (continued) t7256 con?uration (continued) 4. the upstream b-channel source will be either the s/t-interface (if a te has a call active) or the tdm highway (if an analog phone has a call active). each b channel can be sourced from the tdm highway or the s/t-interface independent of the other b chan- nel. the source of the upstream b channels is con- trolled by register dfr0, bits 1 and 0 (for b1) and bits 3 and 2 (for b2). these bits must be controlled dynamically depending on whether an analog phone or a te is requesting the b channel. a sug- gested approach to b-channel control is to default to the s/t-interface (i.e., the tes) and switch to the tdm highway when it is determined that a call is being placed/received on the analog phone (i.e., after call setup has been established via the d channel as described in item #2, above). for exam- ple, if a b1 call is placed on an analog phone, dfr0, bit 1 must be changed from a 1 to a 0 to allow the pots circuitry to source the upstream b1 channel data. all the other bits in dfr0 remain set to 1. register dfr1, bits 5 and 6 control b1 and b2 channel data (respectively) from the u-interface to the tdm highway. it may be necessary to keep the b1 and b2 time slots disabled (3-stated) when the analog phones are not in use to keep the codecs quiet. a 5.1 k w pull-up resistor on the tdmdo pin should be used to ensure that the tdm data is all 1s. some codecs can be quieted by disabling the codec frame strobe signal. 5. when the tdm highway is enabled by setting tdmen = 0, tdmclk and fs will not become active until at least one of the bits 2? in register dfr1 are enabled (set to 0). d-channel priority one issue in this application concerns the d-channel priority mechanism because the d channel must be shared between the ta circuitry and any tes that are connected to the s/t-interface. below is an approach for implementing the d-channel priority mechanism. 1. normally, the d channels from the te should be routed directly through to the switch. thus, the nt1/ ta simply looks like an nt1, passing data directly between the s/t- and u-interfaces. 2. if a pots phone needs to access the d channel (due to an incoming or outgoing call request as described in item #2 of the previous section), it should set sxe = 0 (register gr2, bit 3). this will cause any tes currently accessing the d channel to relinquish the d channel due to a collision detection (i.e., the tes outgoing d bit will differ from its incoming e bit). 3. the pots controller should delay 1.5 ms, then set uxd = 0 (register dfr1, bit 0) to allow local control of the upstream d channel. then it can assume control of the d channel and begin to transmit and receive call control packets via the hdlc formatter. the 1.5 ms delay guarantees that at least seven 1s will be transmitted in the upstream d-channel data stream before the local controller sends the opening ?g of its ?st packet. thus, if the last bit that a te transmitted on the d channel (before sxe = 0 was set) was a 0, the transmission of at least seven 1s will cause an abort hdlc message to be recog- nized by the switch, which properly noti?s the switch that the te that was in the process of send- ing a packet aborted that transmission. 4. when the pots controller has completed its d- channel message, it should set sxe = 1 to relin- quish control of the d channel. more intelligence can be built into the d-channel algo- rithm if desired. for example, since the downstream d- channel messages are always being monitored, it is possible to determine whether a call setup to a te is in progress. if so, the pots controller can hold off a local ta call request until the te call setup is complete. in addition, after each d-channel access, the pots con- troller can allow adequate time for a te to exchange call control messages with a switch before taking over the d channel again. the timing for these sequences would be managed by the ta controller software.
data sheet january 1998 t7256 single-chip nt1 (scnt1) transceiver lucent technologies inc. 61 application briefs (continued) d-channel priority (continued) activation control because there is no guarantee that a te will be con- nected in this application, the local microprocessor must be provisioned to perform a layer-1 activation request as follows: 1. write autoact = 0 (register gr0, bit 6) to initiate start-up on the u-interface. this results in xact = 1 (register cfr1, bit 1). the autoact bit will be set to a 1 automatically after the start-up request is made. this permits another activation attempt by writing autoact = 0 again (without ?st writing it back to 1) if the start-up attempt fails. a switch-initiated start-up is detected by the local microprocessor when xact = 1 (register cfr1, bit 1). this event can be indicated by an interrupt (int, pin 11) by writing the interrupt mask bit ouscm = 0 (register uir1, bit 3) and calling the interrupt routine when uint = 1 (register gir0, bit 0). the ousc interrupt (register uir0, bit 3) indicates a bit change in either cfr1 or cfr2. read these registers to determine which of these bits has changed since the last read. in either of the above cases, it may be necessary to set the sai[1:0] bits in register gr1 to 01. this has the effect of indicating s/t-interface activity to the switch even when no te is attached. some switches require the reception of sai = 1 in order to properly establish layer 1 transparency. 2. look for xact = 0 or oof = 1 (register cfr1, bits 1 and 2). these events can be indicated by an inter- rupt int, pin 11) in a similar manner as described in (1) above. 3. if xact = 0, the start-up attempt has failed and appropriate action should be taken depending on the system requirements (it may be desirable to attempt another start-up). 4. if oof = 1, u-interface synchronization is complete. set actt = 1 (register gr1, bit 4). this will set the upstream act = 1 on the u-interface independent of actions on the s/t-interface. it may be desirable to delay several tens of milliseconds between detecting oof and setting actt = 1 to allow the s/t-interface time to activate if there is a te present. if this is the case, the upstream act bit will automati- cally be set, but manually setting actt = 1 is per- missible. 5. after setting actt = 1, wait for actr = 1 (register cfr1, bit 0). this event can be indicated by an interrupt (int, pin 11) in a similar manner as described in (1) above. the reception of actr = 1, enables u-interface transparency in the upstream direction, so it is not necessary to do so explicitly by setting xpcy = 0 (register gr1, bit 5). at this point, layer-1 activation is complete. note that the above steps 1? occur automatically if there is a te connected or if the lt starts up and sends an eoc loopback-2 request (2b+d loopback). however, having the microprocessor perform these steps ensures layer 1 activation independently of the presence of a te. after layer 1 activation is complete, the xact bit (regis- ter cfr1, bit 1) can be monitored for a state change to 0. this provides an indication to the local microproces- sor that layer 1 has deactivated. when this occurs, set actt = 0 (register gr1, bit 4) to prepare for the next start-up attempt.
data sheet t7256 single-chip nt1 (scnt1) transceiver january 1998 62 lucent technologies inc. application briefs (continued) interfacing the t7256 to the motorola 68302 introduction the motorola mc68302 integrated multiprotocol pro- cessor (imp) contains a 68000 core integrated with a ?xible communications architecture. it has three serial communications controllers (sccs) that can be inde- pendently programmed to support the following proto- cols and physical interfaces. table 31. motorola mc68302 scc options the pcm interface option of the sccs is appropriate for interfacing to the t7256 tdm highway to provide access to b- and d-channel data. the sccs allow isdn b-channel transfers that support applications such as v.120 rate adaption (synchronous hdlc mode) and voice storage (transparent mode). however, the t7256 does not output all signals that are required to connect directly to the scc and some external cir- cuitry (e.g., an epld) is required in order to interface the t7256 tdm highway to the mc68302 scc pcm highway. users of the motorola mc68360 should note that the t7256 can be connected directly to the pcm highway of the mc68360 without the use of any such glue logic. the mc68302 contains a 3-wire serial interface called an scp (serial communications port). the scp may be directly connected to the t7256 serial microprocessor interface to control the t7256 register con?uration. the mc68302 also has programmable ports a (16 bits) and b (12 bits) that are bit-wise programmable and can be used as an alternative to the scp to drive the t7256 serial microprocessor interface. figure 23 illustrates the interface connections between the mc68302 and the t7256. a discussion of the tdm and microprocessor interfaces follows. protocols physical interfaces hdlc/sdlc motorola idl uart gci bisync pcm highway ddcmp nmsi (nonmultiplexed serial interface) v.110 rate adaption transparent 5-4046(c).b figure 23. mc68302 to t7256 interface diagram mc68302 l1sy0 l1sy1 l1clk l1rxd l1txd sprxd sptxd spclk pb0 pb1 pb2 parallel port b signals scp signals pcm mode signals ?or glue logic t7256 fs tdmclk tdmdo tdmdi sdo sdi sck sdo sdi sck microprocessor interface (option #2) microprocessor interface (option #1) tdm interface ckout pa 0 pa 1
data sheet january 1998 t7256 single-chip nt1 (scnt1) transceiver lucent technologies inc. 63 application briefs (continued) interfacing the t7256 to the motorola 68302 (continued) using the motorola mc68302 pcm mode to interface to the t7256 tdm highway in pcm mode, any number of the mc68302 internal sccs can be multiplexed to support a tdm type of interface (see section 4.4.3, pcm highway mode in the mc68302 data book). the sccs in pcm mode require a data-in lead (l1rxd) for receive data, a data-out lead (l1txd) for transmit data, and a common receive and transmit data clock to clock data into and out of the sccs (l1clk). these signals are directly compatible with the t7256 tdm highway. in addition, the pcm- mode sccs require two data synchronization signals, l1sy1 and l1sy0, which route speci? tdm time slots to the sccs. these signals are not directly supported by t7256, and some glue logic is required to generate them. the l1sy0/1 signal pair combinations are used to select between pcm channels 1, 2, and 3 (or to select no pcm channel), where each channel is routed to one of the sccs (routing is controlled by software). they can be set up in an envelope mode such that the they are active for n bits, where n determines the number of bits in a time slot. values of n equal to 7 and 8 are required to interface to the t7256 tdm highway b- channel time slots (for 56 kbits/s or 64 kbits/s data, respectively). a value of n equal to 2 is required to interface to the d-channel time slots. table 32 lists the l1sy0/1 channel assignments for the t7256-to- mc68302 interface circuit. table 32. pcm channel selection the interface circuit can be easily implemented in a programmable logic device. an example is presented here using the altera* epm7032 epld. the epm7032 was selected for this example because it is used on the scnt1 family reference design board (scnt1-rdb) to implement this same function, so the design ?es presented here have already been proven on an actual hardware platform (consult appendix b, scnt1 family reference design board hardware user manual, mn96-011isdn, for detailed design information). the design uses 43% of the epm7032, which leaves a large portion of the device available for other glue func- tions that may be required. if no other system glue is required, the design can be ported to a smaller, cheaper epld. the inputs to the circuit from the t7256 are fs, tdm- clk, and ckout (ckout must be programmed to a frequency of 10 mhz via register gr0, bits 2? in order for the circuit to operate properly). the inputs to the circuit from the 68302 are pa0 and pa1 (parallel port a, bits 0 and 1), which are used to control the 7-bit envelope mode on the b1 and b2 channels. these two signals are called 7bit_b1 and 7bit_b2 in the design ?es and, when set high, enable the 7-bit time-slot mode (otherwise, 8-bit time-slot mode is active). the outputs from the circuit are l1sy0 and l1sy1, which drive the corresponding signals on the 68302. the design was implemented using the altera max+plus ii development system. figures 24, 25, 26, and 27 illustrate the circuit schematic, altera high-level design language (ahdl) ?es, and the timing diagrams for the design. * altera is a registered trademark of altera corporation. l1sy0 l1sy1 channel accessed 0 0 none 1 0 pcm channel 1 (u-interface b1 channel) 0 1 pcm channel 2 (u-interface b2 channel) 1 1 pcm channel 3 (u-interface d channel)
data sheet t7256 single-chip nt1 (scnt1) transceiver january 1998 64 lucent technologies inc. application briefs (continued) interfacing the t7256 to the motorola 68302 (continued) figure 24. scnt1-rdb epld schematic 1st ff stage latches l1sy0/1 on tdmclk falling edge. 2nd ff stage delays l1sy0/1 to meet hold time requirement from tdmclk falling edge to lysy0/1 falling egde. decode logic for l1sy0/1. presets to count=1 on ctr_pre . 8-bit counter. counts on rising tdmclk edge . 7/8-bit control input (56/64 kbps) counter preset circuit. generates pulse for 1/2 tdmclk period at each fs rising edge. 2) the fs strobe should be set active high, enveloping the b1 channel from 1) ckout should be programmed to 10.24mhz (see t7237/56 data shet). notes: means that register tdr0 should be set to 11111111. channel from the u interface (i.e. the 1rd time slot). this means that the purpose of this signal is to keep a stable logic these pins are specified as inputs here to prevent an assignment to them by the compiler. this allows them to "0" level on pin 44 of the epm7032. otherwise, the input would float, which violates altera's design guidelines. be reserved for future use, and ensures that these pins aren't driven when they are not being used. d dff clrn q prn d dff clrn q prn d dff clrn q prn d dff clrn q prn d dff clrn q prn not not and2 302_eplb@17 302_eplb@9 302_eplb@8 gnd 302_eplb@6 302_eplb@41 302_eplb@12 302_eplb@11 302_eplb@7 302_eplb@4 302_eplb@43 302_eplb@1 302_eplb@5
data sheet january 1998 t7256 single-chip nt1 (scnt1) transceiver lucent technologies inc. 65 application briefs (continued) interfacing the t7256 to the motorola 68302 (continued) 8-bit up counter (t-ff based) 8-bit up-counter with async active-high clr. note: ctr_pre sets count = 1. subdesign ctr_8 ( clk, ctr_pre :input; q[7..0] :output; ) variable count[7..0] :dff; begin count[].clk = clk; count[7..1].clrn = !ctr_pre; % counter gets preset to count = 1 on clr % count[0].prn = !ctr_pre; count[] = count[] + 1; q[] = count[]; end; sync decode logic decode logic for frame sync. generates l1sy0/1 logic and shifts them left by 1/2 bit relative to fs. subdesign dec_sync ( cnt[7..0], 7bit_b1, 7bit_b2 input; l1sy0a, l1sy1a output ) begin l1sy0a= # (cnt[] == 0) # (cnt[] == 1) # (cnt[] == 2) # (cnt[] == 3) # (cnt[] == 4) # (cnt[] == 5) # (cnt[] == 6) # ((cnt[] == 7) & !7bit_b1) # (cnt[] == 16) # (cnt[] == 17); l1sy1a= # (cnt[] == 8) # (cnt[] == 9) # (cnt[] == 10) # (cnt[] == 11) # (cnt[] == 12) # (cnt[] == 13) # (cnt[] == 14) # ((cnt[] == 15) & !7bit_b2) # (cnt[] == 16) # (cnt[] == 17); end; figure 25. scnt1-rdb epld ahdl design files
data sheet t7256 single-chip nt1 (scnt1) transceiver january 1998 66 lucent technologies inc. application briefs (continued) interfacing the t7256 to the motorola 68302 (continued) figure 26. scnt1-rdb epld timing (8-bit) [i] 7bit_b1 [i] 7bit_b2 [i] ckout [i] tdmclk [i] fs [o] l1sy1 [o] l1sy0 [b] r_8:26|q[7..0] [b] |ctr_8:26|:52 fe ff 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 125.125us 126.75us 128.375us 130.0us 131.625us 133.25us name:
data sheet january 1998 t7256 single-chip nt1 (scnt1) transceiver lucent technologies inc. 67 application briefs (continued) interfacing the t7256 to the motorola 68302 (continued) figure 27. scnt1-rdb epld timing (7-bit) [i] 7bit_b1 [i] 7bit_b2 [i] ckout [i] tdmclk [i] fs [o] l1sy1 [o] l1sy0 [b] r_8:26|q[7..0] [b] |ctr_8:26|:52 fe ff 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 125.125us 126.75us 128.375us 130.0us 131.625us 133.25us name:
data sheet t7256 single-chip nt1 (scnt1) transceiver january 1998 68 lucent technologies inc. application briefs (continued) interfacing the t7256 to the motorola 68302 (continued) to enable the tdmclk and fs signals and generate the fs signal in the proper time slot, the following t7256 register bits must be programmed: register gr2, bit 5 (tdmen) = 0. register dfr1, bits 7:5 (tdmdu, tdmb2u, tdmb1u) = 000. register tdr0, bit 3:0 (fsp, fsc[2:0]) = 1111 (default). detailed information on t7256 activation control and con?uration of the microprocessor registers can be found in the application briefs, using the t7256 in a combination nt1/ta environment section in this docu- ment. as an example of programming the mc68302 simode register bits for pcm mode, the following settings will enable pcm mode and route the b2 channel to scc1, the b1 channel to scc2, and the d channel to scc3. the isdn signaling protocol stack (q.931 and lapd) would communicate via scc3, and any higher-layer data protocol such as v.120 or v.110 would communi- cate via scc1 and scc2, as required. setz = 0, sync = 1, sdiag1:sdiag0 = 00, sdc2 = 0, sdc1 = 0, b2rb:b2ra = 01, b1rb:b1ra = 10, drb:dra = 11, msc3 = 0, msc2 = 0, and ms1:ms0 = 01. t7256 serial microprocessor interface support the mc68302 scp interface is a 3-wire serial interface that may be directly connected to the t7256 micropro- cessor interface. the scp interface is implemented in the mc68302 hardware, and the only software interac- tion required is to set up the scp interface, to transmit/ receive scp bytes, and to respond to scp events (the scp interrupt). there are several points to note when interfacing the t7256 to the mc68302 microprocessor interface. 1. register bit ci (clock invert) in the mc68302 spmode register should be set to 1 to invert the mc68302 scp clock in order to meet the t7256 microprocessor timing speci?ations. 2. the mc68302 scp clock, spclk, may be pro- grammed to run as high as 4.096 mhz. the mini- mum rate of the scp spclk, assuming the slower 16.384 mhz version of the mc68302 with a maxi- mum divide-down prescale of 64, is 256 khz. the minimum and maximum rates of the t7256 sck are 60 khz and 960 khz, respectively, and care should be taken to ensure that the mc68302 is pro- grammed to a clock rate that is compatible with t7256. 3. every t7256 access consists of two 8-bit transfers, where the ?st is the command/address byte and the second is the data byte. there must be a delay of 10 m s between every 8-bit register access to meet the t7256 microprocessor timing speci?a- tions. the back-to-back byte transmit delay of the mc68302 scp at the slowest spclk rate of 256 khz can be anywhere from two to eight clocks, or 7.8 m s to 31.25 m s. to ensure that the 10 m s delay requirement is met, the mc68302 software must not send the second byte of the 2-byte sequence for at least 10 m s after the scp processor clears the done bit in the scp transmit/receive buffer descriptor (refer to section 4.6.2 of the motorola mc68302 user manual for further information). 4. during 2-byte data transfer over the mc68302 scp, 8 bits will be shifted into the scp receive buffer for every 8 bits shifted out. for a t7256 read, the ?st byte in the receive buffer should be discarded and the second byte will contain the read data from the t7256. for a write, both bytes should be discarded from the scp receive buffer. 5. the t7256 microprocessor interface lacks an enable pin to permit multiple device communication on a single mc68302 scp. in these applications, the t7256 microprocessor interface can be enabled/ disabled using a microprocessor parallel port pin to control a 3-state buffer at sck (pin 15). an alternative method of interfacing the mc68302 to the t7256 microprocessor interface is to use three mc68302 parallel port pins (e.g., pb0, pb1, and pb2 in figure 23) programmed as outputs and supporting the t7256 microprocessor interface in software. the timing of the sck, sdi, and sdo signals can be imple- mented in software with a minimum amount of code.
data sheet january 1998 t7256 single-chip nt1 (scnt1) transceiver lucent technologies inc. 69 application briefs (continued) available tools for evaluation of the t7256 scnt1 family reference design board the scnt1 family reference design board (scnt1- rdb) is a printed-circuit board platform that provides an example implementation of an isdn nt1 circuit based on the lucent t7256 or t7234. in addition, it can be con?ured as an isdn terminal adapter (ta) based on the lucent t7237. with the t7234 or t7256 installed, it is a fully functional nt1, with the exception of power status monitoring circuitry (which can be added by the user). it can be used as an evaluation platform as well as a reference design. with the t7237 installed, it can be used to develop u-interface terminal adapter applications (external control hardware is required in this case). for complete information, con- sult the scnt1 family reference design board hard- ware user manual (document # mn96-011isdn). spec_v2 test board the spec_v2 is a circuit board that connects to a t7256 or t7237-based product in order to provide vari- ous control and status operations. the spec_v2 board is controlled via an rs-232 terminal interface (db-25 connector j2). a pc running a standard termi- nal emulation package can be connected to j2 via one of the pcs com ports. the spec_v2 allows the operations in table 33 to be performed on the unit under test (i.e., the spec_uut). table 33. spec_v2 functions note: optional command-line parameters are shown in brackets. following is an explanation of the command syntax for each command. command-line parameters enclosed in brackets [ ] represent optional parameters. rd ['hex-addr'] read scnt1 register(s). the rd command, when entered with no command line parameters, reads and displays each internal register address and the corresponding contents in the follow- ing format, where the top row (beginning with a:) dis- plays the hexadecimal address and the bottom row (beginning with d:) displays the register data corre- sponding to the address directly above it. for example, if each register contained its address, the resulting dis- play would appear as follows: a:00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 17 18 19 d:00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 17 18 19 when the rd command is entered with the optional command line parameter representing the hexadecimal address of the desired register to read (for example, ?d c ), the resulting display is as follows: addr: 0x0c data: 0xff mon ['hex-addr'] [/s] continuously monitor scnt1 register(s). this command is identical to the rd command, with the following exception?he address and data of the spec- i?d register (or all registers if no ?ex-addr parameter is speci?d) are continuously read and updated on the terminal screen. in addition, there is an optional param- eter, /s, that can be speci?d. this causes each suc- cessive register refresh to appear on a new line (as opposed to the same line). thus, the terminal display will scroll as the values are updated. this can be useful for terminal emulators that have a scrollback buffer, since a history of the register contents and changes is available on screen. to exit this mode, press the esc key. wr 'hex-addr' 'hex-data' write scnt1 register. this command allows ?ex-data to be written to the register at ?ex-addr? for example, to write the value 0xef to register address 0x0a, the following would be entered. wr a ef command function rd ['hex-addr'] read scnt1 register(s) mon ['hex-addr'] [/s] continuously monitor scnt1 register(s) wr 'hex-addr' 'hex-data' write scnt1 register spulse 'pol/mag' enable single pulse mode eye enable eye pattern mode srst perform a h/w reset of scnt1 help display a list of available commands.
data sheet t7256 single-chip nt1 (scnt1) transceiver january 1998 70 lucent technologies inc. application briefs (continued) available tools for evaluation of the t7256 (continued) spulse 'pol/mag' enable single pulse mode. single pulse mode is for performing pulse template tests on the u- and s/t-interfaces. for the u-interface, the chip is placed into a mode in which it periodically (every 125 m s) outputs a single isolated pulse whose magnitude and polarity depend on the ?ol/mag com- mand line parameter, which can be +1, +3, ?, and ?. for the s/t-interface, the i.430-de?ed loop c is set up so that s/t test equipment such as the siemens* k1403 can transmit a ?ed pattern and expect to receive the same pattern (this is a common way of per- forming pulse template tests on the s/t-interface). prior to activating this mode, the u- and s/t-interfaces should be disconnected from the scnt1-based prod- uct until after the mode is entered, at which point they may be reconnected. eye enable eye pattern mode. this mode is for viewing the eye pattern of the received signal at the input to the slicer. this gives a good indi- cation of the receiver performance and shows the effect of impairments such as next. the eye pattern signal is available at bnc connector j5. srst performs a h/w reset of scnt1. help displays a list of available commands. using the spec_v2 to use the spec_v2, connect it to a terminal emulator con?ured for 9600 baud, 8-bit, 1 stop bit, no parity, full duplex, and xon/xoff ?w control. a +5 v supply should be connected to connector j3 using the screw- terminal block provided with the board (the +5 v lead gets connected to pin 1 of j3, and the return lead gets connected to pin 2). when power is applied, led d1 should illuminate to indicate that there is power to the board. once connected to the uut, the spec_v2 should not be powered down, since it may cause the uut to malfunction. spec_v2-to-uut interface description the unit under test (uut) is connected to j1 on the spec_v2 board via one of the two supplied ribbon cable assemblies. if the scnt1-rdb board is being used as the uut, the ribbon cable assembly with the 16-pin ribbon header at both ends can be used and will be connected to the scnt1-rdb at connector j3 (the general-purpose interface). if such a connector is not available on the uut, the ribbon cable assembly with a 16-pin dual header on one end and a plcc-44 ic clip on the other can be used to clip directly to the scnt1 chip on the uut. if the scnt1 is socketed or otherwise not accessible with an ic clip, some other method of access to the required signals must be provided. the j1 connector pinouts are shown in table 34. the j1 signals are assigned such that a straight 16-pin rib- bon cable assembly can be connected directly between j1 of the spec_v2 and the general-purpose interface, j3, of the t7237/56 reference design board (scnt1- rdb). in this case, the signal ckout should be routed through a bnc cable for isolation and shielding. sig- nals that are provided on j3 of the scnt1-rdb but not used by the spec_v2 are noted in the last column. if an alternative cabling arrangement is used, note that the signals in the signal name column must be pro- vided at the uut interface point unless otherwise noted (gnd d need be provided only once). * siemens is a registered trademark of siemens aktiengesellschaft.
data sheet january 1998 t7256 single-chip nt1 (scnt1) transceiver lucent technologies inc. 71 application briefs (continued) available tools for evaluation of the t7256 (continued) important note: in order to use the spec_v2 with your product, you must adhere to the following guidelines: n make sure none of the signals in the signal name column of table 34 are hardwired to v cc or gnd (with the exception of gnd d ). if you need to tie any of these signals high or low, do it through a 5.1 k w resistor. n make sure that circuitry on your board that is driving any of the signal name signals can be disabled (3-stated, open collector output driver turned off, or signal trace cut, if necessary) when using the spec_v2. table 34. spec_v2 interface connector pinouts * if reset is not connected, the t7237/56 will not be reset when exiting mode 2 or 3. if this is the case, the uut must be powered down to get the scnt1 out of test mode. j1 pin # signal name spec_v2 input/ output t7237/ 56 pin # notes 1 gnd d x16 2 connects to v ddd when interfacing to scnt1-rdb. 3 gnd d x10 4 5 sck o 15 6 ckout i 17 7 int i11 8 sdo i 14 9 sdi o 12 10 ps1e i 9 ps1e becomes an output from t7237/56 in test mode. 11 connects to ps2e (t7237/56 pin #8) when interfacing to scnt1_rdb. 12 tdmdi i 7 13 syn8k o 4 14 connects to iloss (t7237/56 pin #6) when interfacing to scnt1- rdb. 15 reset o 43 recommended but not mandatory.* 16 highz i 44 highz becomes an output from t7237/56 in test mode.
data sheet t7256 single-chip nt1 (scnt1) transceiver january 1998 72 lucent technologies inc. application briefs (continued) available tools for evaluation of the t7256 (continued) resetting scnt1 the spec_v2 board has a push-button reset switch (s1) that may be used to reset the 8751 microcon- troller on the spec_v2. asserting reset will restart the spec_v2 ?mware. upon power-on or reset, the spec_v2 displays the opening screen on the terminal, and it appears as follows: lucent technologies spec_v2 control software, v 1.0, 6/2/96 (type "help" (lower case) for a list of commands) at this point, any of the commands in table 33 may be entered. if the current test mode is either single pulse or eye pattern mode, the microcontroller will reset the scnt1 when exiting that mode. this is necessary because the only way to exit these test modes is by resetting scnt1 or cycling the power. the reset is accomplished by pulling the scnt1 reset line (pin 43) low. note that this requires that any device on the uut that drives that reset pin must have an open-drain or 3- statable type of output. if reset cannot be pulled low due to device contention on the uut, the uut must be powered down to get the scnt1 out of test mode. notes on single pulse mode note that, when a single pulse is output on the u-inter- face, the following will be observed: approximately 25 ms after the rising edge of a single positive pulse, a small positive glitch will occur. this is more pronounced on +1 pulses than on +3 pulses, where it is hardly detectable. the cause of the glitch is well understood and was thoroughly investigated during the chip devel- opment to ensure that it causes no harm under normal operating conditions. the explanation is as follows. the transmit sigma-delta modulator in the scnt1 is reset whenever a transi- tion from nonzero data to zero data occurs. it was designed this way for ease of production testing, so that the sigma-delta is always initialized to a known state. this resetting is what causes the glitch. in normal operation, the nonzero to zero case will never occur, except when the transceiver is going from an active state to reset. in this case, there is a control signal that grounds the input to the line driver to force it to transmit 0 v (i.e., forces it into a low-impedance state this feature grew out of the ansi requirements), so the sigma-delta modulator has no effect in this case. thus, the glitch never occurs in normal operation and should be ignored when observing the pulse output. this has been con?med independently at bellcore using their test bed that digitizes the chip output under normal operation, and then reconstructs the pulse shape using dsp ?tering techniques.
data sheet january 1998 t7256 single-chip nt1 (scnt1) transceiver lucent technologies inc. 73 absolute maximum ratings stresses in excess of the absolute maximum ratings can cause permanent or latent damage to the device. these are absolute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those given in the operation sections of the data sheet. exposure to absolute maximum ratings for extended periods can adversely affect device reliability. external leads can be soldered safely at temperatures up to 300 c. handling precautions although protection circuitry has been designed into this device, proper precautions should be taken to avoid expo- sure to electrostatic discharge (esd) during handling and mounting. lucent employs a human-body model (hbm) and charged-device model (cdm) for esd-susceptibility testing and protection design evaluation. esd voltage thresholds are dependent on the circuit parameters used to de?ed the model. no industry-wide standard has been adopted for the cdm. however, a standard hbm (resistance = 1500 w , capacitance = 100 pf) is widely used and, therefore, can be used for comparison. the hbm esd threshold presented here was obtained by using these circuit parameters: recommended operating conditions parameter symbol min max unit dc supply voltage range v dd ?.5 6.5 v power dissipation (package limit) p d 800 mw storage temperature t stg ?5 150 c voltage (any pin) with respect to gnd ?.5 6.5 v esd threshold voltage device voltage t7256-ml2 >1000 t7256-1ml >1000 parameter symbol test conditions min typ max unit ambient temperature t a v dd = 5 v 5% ?0 85 c any v dd v dd 4.75 5.0 5.25 v gnd to gnd v gg ?0 10 mv
data sheet t7256 single-chip nt1 (scnt1) transceiver january 1998 74 lucent technologies inc. electrical characteristics all characteristics are for a 15.36 mhz crystal, 135 w line load, random 2b+d data, t a = ?0 c to +85 c, v dd = 5 v 5%, gnd = 0 v, and output capacitance = 50 pf. power consumption table 35. power consumption pin electrical characteristics table 36. digital dc characteristics (over operating ranges) parameter test conditions min typ max unit power consumption operating, random data 270 350 mw power consumption powerdown mode 35 50 mw parameter symbol test conditions min max unit input leakage current: low high low high i ilpu i ihpu i ilpd i ihpd v il = 0 (pins 2, 6, 7, 11, 44) v ih = v dd (pins 2, 6, 7, 11, 44) v il = 0 (pins 8, 9, 12, 15, 43) v ih = v dd (pins 8, 9, 12, 15, 43) ?2 ?0 ?0 ?0 ?0 ?2 m a m a m a m a input voltage: low high low-to-high threshold high-to-low threshold low high v il v ih v ils v ihs v ilc v ihc all pins except 2, 6, 43 all pins except 2, 6, 43 pin 43 pin 43 pins 2, 6 pins 2, 6 2.0 v dd ?0.5 0.7 v dd 0.8 0.5 0.2 v dd v v v v v v output leakage current: low high low high low high i ozl i ozh i ozlpu i ozhpu i ozlpd i ozhpd v ol = 0, pin 44 = 0 (pins 3, 14) v oh = v dd , pin 44 = 0 (pins 3, 14) v ol = 0, pin 44 = 0 (pin 11) v oh = v dd , pin 44 = 0 (pin 11) v ol = 0, pin 44 = 0 (pins 4, 8, 9, 17) v oh = v dd , pin 44 = 0 (pins 4, 8, 9, 17) ?0 ?2 ?0 10 10 ?0 10 52 m a m a m a m a m a m a output voltage: low, ttl high, ttl v ol v oh i ol = 4.5 ma (pin 3) i ol = 19.5 ma (pins 4, 9) i ol = 8.2 ma (pins 8, 17) i ol = 6.5 ma (pin 14) i ol = 3.3 ma (pin 11) i oh = 32.2 ma (pins 4, 9) i oh = 13.5 ma (pins 8, 17) i oh = 10.4 ma (pins 3, 14) i oh = 5.1 ma (pin 11) 2.4 2.4 2.4 2.4 0.4 0.4 0.4 0.4 0.4 v v v v v v v v v
data sheet january 1998 t7256 single-chip nt1 (scnt1) transceiver lucent technologies inc. 75 electrical characteristics (continued) s/t-interface receiver common-mode rejection table 37. s/t-interface receiver common-mode rejection crystal characteristics table 38. fundamental mode crystal characteristics these are the characteristics of a parallel resonant crystal for meeting the 100 ppm requirements of t1.601 for nt operation. the parasitic capacitance of the pc board to which the t7256 crystal is mounted must be kept within the range of 0.6 pf 0.4 pf. table 39. internal pll characteristics * set by digital pll; therefore, variations track u-interface line rate. parameter symbol specifications unit common-mode rejection (at device pins) cmr 400 mv parameter symbol test conditions specifications unit center frequency f o with 25.0 pf of loading 15.36 mhz tolerance including calibration, temperature stability, and aging tol 70 ppm drive level dl maximum 0.5 mw series resistance r s maximum 20 w shunt capacitance c o 3.0 20% pf motional capacitance c m 12 20% ff parameter test conditions min typ max unit total pull range 250 ppm jitter transfer function ? db point (nt), 18 kft 26 awg 5* hz jitter peaking 1.5 hz typical 1.0* db
data sheet t7256 single-chip nt1 (scnt1) transceiver january 1998 76 lucent technologies inc. timing characteristics t a = ?0 c to +85 c, v dd = 5 v 5%, gnd = 0 v, crystal frequency = 15.36 mhz. for figure 28, assume register tdr0 = f9, dfr1 = 1e, and dfr0 = f5. table 40. tdm bus timing * when connecting the t7256 tdm bus to lucent devices with a chi (concentration highway interface), the chi must be able to withstand 45 ns of bus contention. for this length of time, two devices may be driving the bus. after this time, the output current is less than 10% of the output high and output low currents. the tdmd0 pin on the t7256 was designed to withstand 80 ns of bus contention. 5-4682(c).a figure 28. tdm bus timing ref parameter min typ max unit 1 fs pulse frequency 8 khz 2 tdmclk to fs high 15 ns 3 tdmclk to fs low 15 ns 4 tdmclk frequency 2.048 mhz 5 tdmclk width high 162 230 293 ns 6 tdmclk width low 195 260 326 ns 7 receive (tdmdi) setup time 25 ns 8 receive (tdmdi) hold time 25 ns 9 transmit (tdmdo) time to high impedance 45* ns 10 tdmclk to transmit (tdmdo) valid 50 ns 1 b11 b12 b13 b14 b15 b28 d1 d2 b11 b12 1 2 3 4 5 16 17 18 1 2 b11 b12 b13 b14 b15 b28 d1 d2 b11 b12 4 6 5 8 7 2 10 3 fs tdmclk tdmdo tdmdi 9
data sheet january 1998 t7256 single-chip nt1 (scnt1) transceiver lucent technologies inc. 77 timing characteristics (continued) table 41. clock timing (see figure 29.) * includes the effect of phase steps generated by the digital phase-locked loop. 5-3460 (c) figure 29. timing diagram referenced to syn8k table 42. reset timing 5-3462 (c) figure 30. reset timing diagram symbol parameter min typ max unit syn8k duty cycle 49.8 50.2 % ckout duty cycle: in 15.36 mhz mode in 10.24 mhz mode 40 23* 60 52* % % tr1, tf1 rise or fall time 30 ns tcolfh ckout clock to frame sync (syn8k) 50 ns tr2, tf2 ckout clock rise or fall 15 ns parameter description min max unit trslfl, tflrsh reset setup and hold time 60 ns trslrsh reset low time: from idle mode or normal operation from power-on 375 1.5 m s ms syn8k ckout tcolfh tr1 tr2 tf2 tf1 syn8k reset trslfl tflrsh trslrsh
data sheet t7256 single-chip nt1 (scnt1) transceiver january 1998 78 lucent technologies inc. timing characteristics (continued) switching test input/output waveform 5-2118 (c) figure 31. switching test waveform figure 31 assumes that pin 12 (sdi) is low when reset is asserted. the meaning of the setup and hold times trslfl and tflrsh is as follows. from the time reset goes low, the following events must occur: 1. a falling edge of syn8k must occur that meets the setup time with respect to reset falling edge. 2. at least two additional falling edges of syn8k (i.e., frames) must occur. 3. a falling edge of syn8k must occur that meets the hold time with respect to reset rising edge. if reset is asserted asychronously to syn8k (which will typically be the case), its falling edge may violate the setup time with respect to syn8k. therefore, an additional frame time (125 m s) will elapse before a falling edge of syn8k occurs that will satisfy criterion #1, above. this means, that to guarantee the reset requirements are met for parameter trslrsh, reset should be held low for a minimum of 500.120 m s (4 frames + 1 setup time + 1 hold time). propagation delay the maximum propagation delay from the s/t-interface to the u-interface (upstream direction) is 750 m s. the maximum propagation delay from the u-interface to the s/t-interface (downstream direction) is 550 m s. 2.0 v 0.8 v 2.0 v 0.8 v test points 2.4 v 0.4 v 2.4 v 0.4 v
data sheet january 1998 t7256 single-chip nt1 (scnt1) transceiver lucent technologies inc. 79 outline diagram 44-pin plcc controlling dimensions are in inches. 5-2506r8 note: the dimensions in this outline diagram are intended for informational purposes only. for detailed schematics to assist your design efforts, please contact your lucent technologies sales representative. ordering information device code shipping method package temperature reliability comcode t7256- - -ml2-d dry pack?ticks 44-pin plcc ?0 c to +85 c 300 ppm 107177065 t7256- - -ml2-dt dry pack?ape & reel 44-pin plcc ?0 c to +85 c 300 ppm 107231672 t7256a - -ml-d dry pack?ticks 44-pin plcc ?0 c to +85 c 107997413 t7256a - -ml-dt dry pack?ape & reel 44-pin plcc ?0 c to +85 c 108051806 1.27 typ 0.330/0.533 0.10 seating plane 0.51 min typ 4.572 max 1 640 7 17 29 39 18 28 pin #1 identifier zone 16.586 0.076 17.526 0.127 16.586 0.076 17.526 0.127
data sheet t7256 single-chip nt1 (scnt1) transceiver january 1998 80 lucent technologies inc. questions and answers introduction this section is intended to answer questions that may arise when using the t7256 single-chip nt1 trans- ceiver. the questions and answers are divided into three cate- gories: u-interface, s/t-interface, and miscellaneous. u-interface q1: is the line interface for the t7256 the same as for the t7264? a1: yes. the u-interface section on these chips is identical, so their line interfaces are also identical. q2: why is a higher transformer magnetizing induc- tance used (as compared to other vendors)? a2: it has been determined that a higher inductance provides better linearity. furthermore, it has been found that a higher inductance at the far end pro- vides better receiver performance at the near end and better probability of start-up at long loop lengths. q3: can the t7256 be used with a transformer that has a magnetizing inductance of 20 mh? a3: the echo canceler and tail canceler are opti- mized for a transformer inductance of approxi- mately 80 mh and will not work with lower inductance transformers. q4: are the lucent technologies u-interface trans- formers available as surface-mount components? a4: not at this time. q5: are there any future plans to make a smaller height 2-wire transformer? a5: due to the rigid design speci?ations for the transformer, vendors have found it dif?ult to make the transformer any smaller. we are con- tinuing to work with transformer vendors to see if we can come up with a smaller solution. q6: the line interface components speci?ations require 16.9 w resistors on the line side of the transformer when using the 2754h2. for our application, we would like to change this value. can the u-interface line-side circuit be rede- signed to change the value of the line-side resis- tors? a6: yes. for example, the line-side resistances can be re?cted back to the device side of the trans- former so that, instead of having 16.9 w on each side of the transformer, there are no resistors on the line side of the transformer and 24.4 w resis- tors on the device side (16.9 w + 16.9 w /n 2 , where n is the turns ratio of the transformer). note that the re?cted resistances should be kept separate from the device-side 16.9 w resistors, and located between vr1 and t1 in figure 20. this is necessary because the on-chip hybrid network (pins hp, hn) is optimized for 16.9 w of resistance between it and the lop/lon pins. q7: table 29, t7256 reference schematic parts list, states the 0.1 m f capacitor that is used with the lh1465 (c15) must have an insulation resistance of >2 g w . why? a7: this capacitor is used to set the gate/source volt- age for the main transistor in the device. the charging currents for this capacitor are on the order of microamps. since the currents are so small, it is important to keep the capacitor leak- age to a minimum. q8: the dc blocking capacitor (c16 in figure 20) speci?d is 1.0 m f. can it be increased to at least 2 m f? a8: this value can be increased to 2 m f without an effect on performance. however, for an nt1 to be compliant with t1.601-1992 section 7.5.2.3, the dc blocking capacitor must be 1.0 m f 10%. q9: why is the voltage rating on 1 m f dc blocking capacitor (c16 in figure 20) so high (250 v)? a9: in appendix b of t1.601, the last section states that consideration should be given to the handling of three additional environmental conditions. the third condition listed is maximum accidental ring- ing voltages of up to ?00.5 v peak whose cadence has a 33% duty cycle over a 6 s period.
data sheet january 1998 t7256 single-chip nt1 (scnt1) transceiver lucent technologies inc. 81 questions and answers (continued) u-interface (continued) a9: (continued) this statement could be interpreted to mean that a protector such as vr2 in figure 20 should not trip if subjected to a voltage of that amplitude. this interpretation sets a lower limit on vr2s breakover rating. since capacitor c16 will be exposed to the same voltage as vr2, its voltage rating must be greater than the maximum break- over rating of vr2. this sets an upper limit on the protector breakover voltage. the result is a need for a capacitor typically rated at about 250 v. however, an argument can be made that it doesn? matter whether vr2 trips under this con- dition, since it is a fault condition anyway, and a tripped protector won? do any damage to a cen- tral of?e ringer. the only other similar requirement, then, is found in footnote 8, referenced in section 7.5.3 of ansi t1.601. the footnote implies that the maximum voltage that an nt will see during metallic testing is 90 v. the breakover voltage vr2 must be large enough not to trip during the application of the test voltage mentioned in the footnote. this means that a protector with a minimum breakover voltage of 3 90 v can be used that would permit a capacitor of lower voltage rating (e.g., 150 v) to be used. this is the approach we currently favor, although figure 20 illustrates the more conserva- tive approach. q10: what is the purpose of the 3300 pf capacitors (c13 and c14) in figure 20 in the data sheet? a10: the capacitors are for common-mode noise rejection. the ansi t1.601 speci?ation contains no requirements on longitudinal noise immunity. therefore, these capacitors are not required in order to meet the speci?ation. however, there are guidelines in iec 801-6 which suggest a noise immunity of up to 10 vrms between 150 khz and 250 mhz. at these levels, the 10 khz tone detector in the t7256 may be desen- sitized such that tone detection is not guaranteed on long loops. the 3300 pf was selected to pro- vide attenuation of this common-mode noise so that tone detector sensitivity is not adversely affected. since the 3300 pf capacitor was selected based only on guidelines, it is not man- datory, but it is recommended in applications which may be susceptible to high levels of com- mon-mode noise. the ?al decision depends on the speci? application. as for the size of the capacitors, lab tests indicate the following: 1. the performance of the system suffers no degradation until the values are increased to about 0.1 m f. 2. the return loss at 25 khz increases with increasing capacitor value. 3. the capacitor value has no effect on longitudi- nal balance. 4. a large unbalance in the capacitor values did not affect return loss, longitudinal balance, or performance. q11: are there any recommended common-mode ?- tering parts for the u-interface? i suspect that our product may have emissions problems, and i want to include a provision for common-mode ?- tering on the u-interface. a11: the only common-mode ?tering parts we have any data on are two common-mode chokes from pulse engineering ( 619-674-8100 ) that are intended to help protect against external com- mon-mode noise. the part numbers are pe-68654 (12.5 mh) and pe-68635 (4.7 mh), and in lab experiments, no noticeable degrada- tion in transmission performance was observed. these chokes are typically effective in the fre- quency range 100 khz? mhz. as far as emissions are concerned, we don? have a lot of data. we have seen some success with the use of rj-45 connectors that have integral ferrite beads such as those from corcom*, inc., (708) 680-7400. these provide some ?xibility in that they have the same footprint as some stan- dard rj-45 connectors. * corcom is a registered trademark of corcom, inc.
data sheet t7256 single-chip nt1 (scnt1) transceiver january 1998 82 lucent technologies inc. questions and answers (continued) u-interface (continued) q12: i am planning on using a raychem ptc (p/n tr600-150) on the u-interface of the t7256 as shown in figure 20. the device is rated at 6 w ?2 w . i am concerned about the loose toler- ance on the ptc resistance. will i be able to pass the return loss requirements in ansi t1.601 sec- tion 7.1? a12: the nt1 impedance limits looking into tip/ring are derived from the t1.601 return loss requirements (figure 17 in t1.601). at the narrowest point in the templates, the permissible range is between 111 w to 165 w . the tolerance on the ptc will reduce the impedance margin somewhat, but should still be acceptable. figure 32 is derived from the return loss template in ansi t1.601. return loss is a measure of the match between two impedances on either side of a junction point. the following equation is an expression of return loss in terms of the complex impedances of the two halves of the circuit z 1 , z 2. rl (db) = 20 log when the impedances are not matched, the junc- tion becomes a reflection point. for a perfectly matched load, the return loss is infinite, whereas for an open or short circuit, the return loss is zero. the return loss expresses the ratio of incident to reflected signal power and should consequently be fairly high. z 1 z 2 + z 1 z 2 ------------------- - 5-4056 (c) figure 32. transceiver impedance limits 10000 1000 100 10 1 1.0 1.4 2.0 2.8 4.0 5.6 7.9 11.2 15.8 22.4 31.6 44.7 63.1 89.1 125.9 177.8 251.2 impedance ( w ) frequency (khz) upper bound > 165 w lower bound < 110.4 w
data sheet january 1998 t7256 single-chip nt1 (scnt1) transceiver lucent technologies inc. 83 questions and answers (continued) u-interface (continued) a12: (continued) it is desirable to express the return loss in terms of im- pedance bounds, since an impedance measurement is relatively simple to make. from the above equation, up- per and lower bounds on impedance magnitude can be derived as follows: z o = return loss reference impedance = 135 w z u = upper impedance curve z l = lower impedance curve upper bound (z u > z o ) : rl (db) = 20 log lower bound (z l < z o ): rl (db) = 20 log note that the higher the minimum return loss require- ment, the tighter the impedance limits will be around z o , and vice versa. so, for the upper bound, solve for z u : for the lower bound, solve for z l : plotting the above equations (using 135 for zo and fig- ure 16 in t1.601 for the rl values) results in the graph shown in figure 32, which shows the return loss expressed in terms of impedance upper and lower bounds. q13: why must secondary protection, such as a sgs- thomson sm6t6v8ca protection diode, be used? a13: the purpose of the diode is to protect against metallic surges below the breakdown level of the primary protector. such metallic surges can be coupled through the transformer and could cause device damage if the currents are high. the protector does not pro- vide absolute protection for the device, but it works in conjunction with the built-in protection on the device leads. the breakdown voltage level for secondary pro- tection devices must be chosen to be above the normal working voltage of the signal and typically below the breakdown voltage level of the next stage of protection. the sm6t6v8ca has a mini- mum breakdown voltage level of 6.4 v and a maximum breakdown voltage of 7.1 v. the chip pins that the sm6t6v8ca protects are pins 36 (hp), 31 (hn), 32 (lop), and 35 (lon). the 16.9 w resistors will help to protect pins 32 and 35, but pins 31 and 36 will be directly exposed to the voltage across the sm6t6v8ca. the on-chip protection on these pins consists of output diodes and a pair of polysilicon resistors. these pins have been thoroughly tested to ensure that a 7.1 v level will not damage them; therefore, no third level of protection is needed between the sm6t6v8ca and the hp and hn pins. the sm6t6v8ca has a maximum reverse surge voltage level of 10.5 v at 57 a. sustained cur- rents this large on the device side of the trans- former are not a concern in this application. thus, there should never be more than 7.1 v across the sm6t6v8ca, except for possibly an esd or lightning hit. in these cases, the t7256 is able to withstand at least 1000 v (human-body model) on its pins. z o z u + z u z o --------------------- z o z l + z u z l -------------------- z u z o 10 rl 20 ------- - 1 + 10 rl 20 ------- - 1 ---------------------- - ? ? ? ? ?? z o 110 rl 20 ---------- - + 110 rl 20 ---------- - ------------------------- - ? ? ? ? ?? = = z u z o 10 rl 20 ------- - 1 10 rl 20 ------- - 1 + ------------------------ ? ? ? ? ?? z o 110 rl 20 ---------- - 110 rl 20 ---------- - + -------------------------- - ? ? ? ? ?? = =
data sheet t7256 single-chip nt1 (scnt1) transceiver january 1998 84 lucent technologies inc. questions and answers (continued) u-interface (continued) q14: where can information be obtained on lightning and surge protection requirements for 2b1q products? a14: requirements vary among applications and between countries. ansi t1.601, appendix b, provides a list of applicable speci?ations to which you may refer. also, there are many manu- facturers of overvoltage protection devices who are familiar with the speci?ations and would be willing to assist in surge protection design. the itu-t k series recommendations are also a good source of information on protection, especially recommendation k.11, ?rinciples of protection against overvoltages and overcurrents, which presents an overview of protection principles. also refer to the application notes mentioned in the u-interface description section of this data sheet. q15: itu-t speci?ation k.21 describes a lightning surge test for nt1s (see figure 1/k.21 and table 1/k.21, test #1) in which both tip and ring are connected to the source and a 1.5 kv voltage surge is applied between this point and the gnd of the nt1. what are the protection consider- ations for this test? are the hp and hn pins sus- ceptible to damage? a15: the critical component in this test is the trans- former since its breakdown voltage must be greater than 1.5 kv. assuming this is the case, the only voltage that will make it through to the secondary side of the transformer will be prima- rily due to the interwinding capacitance of the transformer coils. this capacitance will look like an impedance to the common-mode surge and will therefore limit current on the device side of the transformer. the device-side voltage will be clamped by the sm6t6v8ca device. the maxi- mum breakdown voltage of the sm6t6v8ca is 7.1 v. the 16.9 w resistors will help protect the lop and lon pins on the t7256 from this volt- age. however, this voltage will be seen directly on pins 36 and 31 (hp and hn) on the t7256. the on-chip protection on these pins consists of out- put diodes and a pair of polysilicon resistors. these pins have been thoroughly tested to ensure that an 7.4 v level will not damage them; therefore, no third level of protection is needed between the sm6t6v8ca and the hp and hn pins. q16: can the range of the t7256 on the u-interface be speci?d in terms of loss? what is the range over straight 24 awg wire? a16: ansi standard t1.601, section 5.1, states that transceivers meeting the u-interface standard are intended to operate over cables up to the limits of 18 kft (5.5 km) 1300 w resistance design. resis- tance design rules specify that a loop (of single- or mixed-gauge cable; e.g., 22 awg, 24 awg, and 26 awg) should have a maximum dc resistance of 1300 w , a maximum working length of 18 kft, and a maximum total bridged tap length of 6 kft. the standard states that, in terms of loss, this is equivalent to a maximum insertion loss of 42 db @ 40 khz. lucent technologies has found that, for assessing the condition of actual loops in the ?ld in a 2b1q system, specifying insertion loss as 33.4 db @ 20 khz more closely models ansi circuit operation. this is equivalent to a straight 26 awg cable with 1300 w dc resistance (15.6 kft). the above goals are for actual loops in the out- side loop plant. these loops may be subjected to noise and jitter. in addition, as mentioned above, there may be bridge taps at various points on the loop. the t1.601 standard de?es 15 loops, plus the null, or 0-length loop, which are intended to represent a generic cross section of the actual loop plant. a 2b1q system must perform over all of these loops in the presence of impairments with an error rate of <1e?. loop #1 (18 kft, where 16.5 kft is 26 awg cable and 1.5 kft is 24 awg cable) is the longest, so it has the most loss (37.6 db @ 20 khz and 47.5 db @ 40 khz). note that this is more loss than discussed in the pre- ceding paragraph. the difference is based on test requirements vs. ?ld deployment. the test requirements are somewhat more stringent than the ?ld goal in order to provide some margin against severe impairments, complex bridged taps, etc.
data sheet january 1998 t7256 single-chip nt1 (scnt1) transceiver lucent technologies inc. 85 questions and answers (continued) u-interface (continued) a16 : (continued) if a transceiver can operate over loop #1 error- free, it should have adequate range to meet all the other loops speci?d in t1.601. loop #1 has no bridged taps, so passing loop #1 does not guarantee that a transceiver will successfully start up on every loop. also, due to the complex nature of 2b1q transceiver start-up algorithms, there may be shorter loops which could cause start-up problems if the transceiver algorithm is not robust. the t7256 has been tested on all of the ansi loops per the t1.601 standard and passes them all successfully. two loops com- monly used in the lab to evaluate the perfor- mance of the t7256 silicon are as follows: the t7256 is able to start up and operate error- free on both of these loops. neither of these loops is speci?d in the ansi standard, but both are useful for evaluation purposes. the ?st loop is used because it is simple to construct and easy to emulate using a lumped parameter cable model, and it is very similar to ansi loop #1, but the loss is slightly worse. thus, if a transceiver can start up on this loop and operate error-free, its range will be adequate to meet the longest ansi loop. the second loop is used because, due to its dif?ult bridge tap structure and its length, it stresses the transceiver start-up algo- rithms more than any of the ansi-de?ed loops. therefore, if a transceiver can start up on this loop, it should be able to meet any of the ansi- de?ed loops which have bridge taps. also, on a straight 26 awg loop, the t7256 can successfully start up at lengths up to 21 kft. this fact, com- bined with reliable start-up on the 15 kft 2bt loop above, illustrates that the t7256 provides ample start-up sensitivity, loop range, and robustness on all ansi loops. another parameter of interest is pulse height loss (phl). phl can be de?ed as the loss in db of the peak of a 2b1q pulse rela- tive to a 0-length loop. for an 18 kft 26 awg loop, the phl is about 36 db, which is 2 db worse than on ansi loop #1. a signal-to-noise ratio (snr) measurement can be performed on the received signal after all the signal processing is complete (i.e., at the input to the slicer in the decision feed- back equalizer). this is a measure of the ratio of the recovered 2b1q pulse height vs. the noise remaining on the signal. the snr must be greater than 22 db in order to operate with a bit error rate of <1e?. with no impairments, the t7256 snr is typically 32 db on the 18 kft/26 awg loop. when all ansi-speci?d impairments are added, the snr is about 22.7 db, still leaving adequate margin to guaran- tee error-free operation over all ansi loops. finally, to estimate range over straight 24 awg cable, the 18 kft loop loss can be used as a limit (since the t7256 can operate successfully with that amount of loss) and the following calcula- tions can be made: thus, the operating range over 24 awg cable is expected to be about 24 kft. q17: what does the energy spectrum of a 2b1q signal look like? a17: figure a1 (curve p1) in the ansi t1.601 stan- dard illustrates what this spectrum looks like. loop configuration bridge taps (bt) loss @ 20 khz (db) loss @ 40 khz (db) 18 kft/26 awg none 38.7 49.5 15 kft/26 awg two at near end, each 3 kft/22 awg 37.1 46.5 loss of 18 kft/26 awg loop @ 20 khz 38.7 db loss per kft of 24 awg cable @ 20 khz 1.6 db 38.7 db 1.6 db / kft --------------------------- - 24 kft =
data sheet t7256 single-chip nt1 (scnt1) transceiver january 1998 86 lucent technologies inc. questions and answers (continued) u-interface (continued) q18: please clarify the meaning of ansi standard t1.601, section 7.4.2, jitter requirement #3. a18: the intent of this requirement is to ensure that after a deactivation and subsequent activation attempt (warm start), the phase of the receive and transmit signals at the nt will be within the speci?d limits relative to what they were prior to deactivation. this is needed so that the lt, upon a warm-start attempt, can make an accurate assumption about the phase of the incoming nt signal with respect to its transmit signal. note that the t7256 meets this requirement by design because the nt phase offset from transmit to receive is always ?ed. q19: i need a way to generate a scrambled 2b1q data stream from the t7256 for test purposes (e.g., ansi t1.601 section 5.3.2.2, total power and section 7.2, longitudinal output voltage). how can i do this? a19: a scrambled 2b1q data stream (the ?n1 signal described in ansi t1.601 table 5) can be gener- ated by pulling iloss (pin 6) low on the t7256. q20: we are trying to do a return loss measurement on the u-interface of the t7256 per ansi t1.601 section 7.1. we are using a circuit similar to the one you recommend in the data sheet. we have observed the following. when the chip is in full reset mode (powered on but no activity on the u- or s/t-interfaces), the return loss is very low, i.e., the termination impedance appears to be very large relative to 135 w and falls outside the boundaries of figure 19 of ansi t1.601. how- ever, if we inject a 10 khz tone before making a measurement, the return loss falls within the tem- plate. why is it necessary to inject the 10 khz tone in order to get this test to pass? shouldn? a 135 w impedance be presented to the network regardless of the state of the t7256 once it is powered on? a20: the return loss is only relevant when the trans- mitter section is powered on. when the transmit- ter is powered, it presents a low-impedance output to the u-interface. the transmitter must be held in this low-impedance state when the return loss and longitudinal balance tests are per- formed. this can be accomplished by pulling reset low (pin 43). with the reset pin held low, the transmitter is held in a low-impedance state where each of its differential outputs drives dv. in this state, it is prevented from transmitting any 2biq data and won? respond to any incom- ing wakeup tones. this is different than the ansi- de?ed full reset state that the chip enters after power-on or deactivation. in full reset, the transmitter is powered down and in a high- impedance state, with only the tone detector powered on and looking for a far-end wakeup tone. the transmitter powers down when in full reset state to save power and maximize the tone detector sensitivity. the reason that the chip behaves as it does in your tests is that your test begins with the transmitter in its full reset state, causing the return loss to be very low. if a 10 khz signal is applied, the tone detector senses the applied signal and triggers. this causes the transmitter to enter its low-impedance state, where it will remain until the t7256 start-up state machine times out (typically within 1.5 sec- onds, depending on the signal from the far end). q21: what are the average cold start and warm start times? a21: lab measurements have shown the average cold start time to be about 3.3 s?.2 s over all loop lengths, and the average warm-start time to be around 125 ms?90 ms over all loop lengths. q22: what is the u-interfaces response time to an incoming wakeup tone from the lt? a22: response time is about 1 ms. q23: what is the minimum time for a u-interface reframe after a momentary (<480 ms) loss of syn- chronization? a23: five superframes (60 ms). q24: where is the u-interface loopback 2 (i.e., eoc 2b+d loopback) performed in the t7256? a24: it is performed just inside the chip at the s/t-inter- face. the s/t receiver is disconnected internally from the chip pins, and the s/t transmit signal is looped back to the receiver inputs so the s/t sec- tion synchronizes to its own signal. this ensures that as much of the data path as possible is being tested during the 2b+d loopback. q25: are the embedded operations channel (eoc) ini- tiated b1 and b2 channel loopbacks transparent? a25: yes, the b1 and b2 channel loopbacks are trans- parent, as is the 2b+d loopback.
data sheet january 1998 t7256 single-chip nt1 (scnt1) transceiver lucent technologies inc. 87 questions and answers (continued) u-interface (continued) q26: how can proprietary messages be passed across the u-interface? a26: the embedded operations channel (eoc) pro- vides one way of doing this. ansi standard t1.601 de?es 64 8-bit messages which can be used for nonstandard applications. they range in value from binary 00010000 to 01000000. there is also a provision for sending bulk data over the eoc. setting the data/message indicator bit to 0 indicates the current 8-bit eoc word con- tains data that is to be passed transparently with- out being acted on. note that there is no response time requirement placed on the nt in this case (i.e., the nt does not have to echo the message back to the lt). also note that this is currently only an ansi provision and is not an ansi requirement. the t7256 does support this provision. q27: what is the value of the ansi t1.601 cso and nib bits in the 2b1q frame? a27: cso and nib are ?ed at 0 and 1, respectively, by the device. this is because the device always has warm start capability (cso = 0), and nt1s are required to have nib = 1 per t1.601-1992. q28: are the ps bits controllable from outside the chip? a28: yes, the bits are controlled by two pins (8 and 9) on the chip. when the t7256 tdm highway is enabled, these pins change function and become part of the tdm highway and ps1 and ps2 are controlled by register gr1, bits 1 and 2. q29: it looks like the u-interface sai and act bits that the t7256 transmits towards the lt always track one another. if this is the case, i don? understand why they are both needed. can you explain the purpose of the sai bit and how it relates to the act bit? a29: the sai bit is equal to 1 when there is activity (info 1 or info 3) on the s/t-interface. the act bit is 1 whenever layer 1 transparency is estab- lished. most of the time these bits are the same, but there are two situations where they will be dif- ferent. 1. the sai bit can be used in conjunction with the uoa bit from the lt to support dsl-only activa- tion as described in the ansi and etsi stan- dards. the lt can request a u-only activation by setting uoa = 0, which will cause the s/t-interface to remain in a deactivated state. if the te requests an activation under these conditions by transmitting info 1 to the t7256, the sai bit will change from 0 to 1, indicating to the lt that there is activity on the s/t-interface so that the lt can respond accordingly. typically, this means that lt will set uoa = 1 to exit the dsl-only condition so that layer-1 transparency can be established from te to lt. thus, in the case of a dsl-only activation, the t7256's sai bit is 1 and its act bit is 0 from the time a te requests an activation until the following events occur: a. lt sets uoa = 1 towards the nt. b. the t7256 detects uoa = 1 and transmits info 2 on the s/t-interface. c. the te synchronizes and transmits info 3 on the s/t-interface. d. upon reception of the info 3 signal, the t7256 sets act = 1. 2. if a link is fully active, then the lt detects a transition of the nt act bit from 1 to 0, it is an indication of loss of layer-1 transparency. this can be caused by either a) s/t loss of sync or b) nt1 received info 0. case a) will result in an act = 0/sai = 1 combination, i.e., s/t sync is lost but there is still activity on the s/t-inter- face, meaning the te is having trouble staying synchronized. case b) will result in an act = 0/sai = 0 combination, i.e., no activity on the s/t-interface (info 0), meaning the te has been disconnected (there is no way the te can legally send info 0 when the link is fully active because the te is not allowed to initiate deac- tivation?nly the lt is?o the only other pos- sibility is that it has been disconnected or has failed). note that this procedure allows the co to determine whether the cause of loss of layer 1 transparency is a te that is having synchro- nization problems or a te that has been dis- connected, based on the state of the sai bit when act = 0. the ansi t1.601 and etsi etr 080 stan- dards contain finite state matrices that de- scribe dsl-only operation. the t7256 follows the behavior described in the matrices. refer to those tables for detailed information on each of the states.
data sheet t7256 single-chip nt1 (scnt1) transceiver january 1998 88 lucent technologies inc. questions and answers (continued) s/t-interface q30: what is the s/t transformers inductance? a30: for lucent transformers 2768a or 2776, a mini- mum inductance of 22 mh is guaranteed. q31: we are trying to test the s/t side of our t7256- based nt1 using a siemens k1403 isdn tester. the tester is not able to sync up to the nt1. can you explain this behavior? a31: check the connector wiring of the s/t-interface. in the january 1995 t7256 data sheet, the pinouts of the rj-45 s/t connector (j1) were shown incorrectly. the ones shown are for a te. the correct (i.e., nt) pinouts are listed in the cur- rent t7256 data sheet (swap pins 3 and 6 with pins 4 and 5, respectively). if the pinout is wrong as just described, the siemens k1403 will not sync up to the s/t-interface. q32: can the s/t-interface leads be short-circuited together without harming the device? a32: yes, this will not cause any harm to the device. q33: what is the common-mode rejection of the s/t receiver? a33: the common-mode rejection of the s/t receiver is 400 mv. refer to the electrical characteristics described in the data sheet. q34: i notice that the application note entitled design an s/t line interface circuitry using the t7250c/ t7259 recommends relays on both the transmit- ter and receiver outputs that disconnect the device when power is removed from the chip. is this necessary for an nt using the t7256? a34: the relay on the te transmitter output is neces- sary to pass the peak current test (itu-t i.430 section 8.5.1.2 and ansi t1.605-1991, section 9.5.1.2) when the te is powered down. for the nt, there is no equivalent test, so the relay is not necessary. the relay on the te receiver input is also necessary to pass the peak current test (itu-t i.430 sections 8.5.1.2 and 8.6.1.1, and ansi t1.605-1991 sections 9.5.1.2 and 9.6.1.1). for the nt, however, there is enough margin in the line interface capacitance circuitry such that the peak current requirement (itu-t i.430 sec- tion 8.6.1.2 and ansi t1.605-1991 section 9.6.1.2) can be met without using relays. this assumes, of course, that sound layout practices have been applied to keep parasitic capacitance of the line interface circuitry to a minimum (of pri- mary importance is making sure there is no ground plane under the s/t line interface). the reason the te needs a relay on its receiver is that the te tests assume a 350 pf cord connected to the line, and this extra capacitance can cause the peak current requirement to be exceeded. so even though the nt peak current requirement is slightly more stringent (0.5 ma as opposed to 0.6 ma), the te peak current test is the most dif? cult to meet due to the 350 pf cord capacitance. q35: the t7256 reference design in figure 21 shows 100 w termination resistors in parallel with a sec- ond pair of optional 100 w resistors that can be inserted or removed by installing/removing jump- ers from jmp1 and jmp2. what is the purpose of this second pair of resistors? a35: typically, a te or group of tes connected to an nt1 will have a 100 w termination located at the interface point of the te farthest from the nt1 (refer to itu-t i.430 figure 2 and section 4 or t1.605 figure 2 and section 5). however, in some cases it may be desirable to operate an nt1 with a te that does not provide the 100 w termination impedance. in this case, the provi- sional 100 w resistors shown in figure 21 may be installed to provide the extra termination imped- ance required.
data sheet january 1998 t7256 single-chip nt1 (scnt1) transceiver lucent technologies inc. 89 questions and answers (continued) s/t-interface (continued) q36: i would like to integrate a t7256-based nt1 onto both a t7250c-based 4-wire te product and a t7903-based 4-wire te product in order to pro- vide a u-interface on these products. i realize this can be done by simply incorporating my external nt1 design directly onto the te board, but is there a simpler approach in which i can avoid having two sets of s/t transformers and associ- ated line interface circuitry? a36: yes. first note figures 34, 35, and 36, which show example s/t line interface circuits for the t7256, t7903, and t7250c, respectively. if no external s/t-interface connection is required, the t7256 can be directly connected to the t7903 and t7250c as shown in figures 37 and 38. if there is a requirement for connecting external tes, the circuits shown in figures 39 and 40 can be used. these two circuits show a hybrid scheme in which a direct connect between the t7256 and t7903/t7250c is implemented while providing for an external s/t-interface (thus requiring only one set of s/t transformers rather than the two sets that would be required if the t7256 and t7903/t7250c were transformer-cou- pled to one another instead directly connected). the direct connect circuits were derived as shown in figures 37 and 38 and the following text sections: note: in all of these analyses, the ?al value of resistance chosen may be slightly differ- ent than the ideal value computed because standard resistance values were used. t7903/t7250c transmit to t7256 receive a) transmitter load: t7903: the line interface transformer has a turns ratio of 2.0, and the transmitter drives a total line-side load of 50 w . re?cting this impedance to the device side of the trans- former results in 200 w (50 w x n 2 ). this resistance, combined with the 40 w total resistance of the device-side resistors, results in a total of 240 w that the transmitter typically drives. so, to optimize the transmitter part of the cir- cuit based on the load the transmitter expects to drive, the transmitter should see a total resistance of approximately 240 w . t7250c: the line interface transformer has a turns ratio of 2.5, and the transmitter drives a line-side load of 50 w . re?cting this imped- ance to the device side of the transformer results in 312.5 w (50 w x n 2 ). this resis- tance, combined with the 113 w total resis- tance of the device-side resistors, results in a total of 425.5 w that the transmitter typically drives. so, to optimize the transmitter part of the circuit based on the load the transmitter expects to drive, the transmitter should see a total resistance of approximately 425 w .
data sheet t7256 single-chip nt1 (scnt1) transceiver january 1998 90 lucent technologies inc. questions and answers (continued) s/t-interface (continued) a36: (continued) b) receiver levels: the t7256 s/t line interface transformer has a turns ratio of 2.5. the receiver expects to see nominal pulse levels of 750 mv x 2.5 = 1.875 v. t7903: the transmitter circuit is a current source of 7.5 ma. to generate a voltage of 1.875 v with 7.5 ma requires a resistance of 1.875/0.0075 = 250 w . t7250c: the transmitter circuit is a current source of 6 ma. to generate a voltage of 1.875 v with 6 ma requires a resistance of 1.875/0.006 = 312.5 w . c) resistor selection: in this section, the term receiver implies not only the receive section on the chip, but also the external 10 k w resistors connected to the receiver. these resistors remain unchanged from the standard line interface circuit in order to maintain the same total receiver impedance. t7903: ideally, the transmitter should be driv- ing into 240 w , and the t7256 receiver wants to see the levels that would result if the trans- mitter drove 7.5 ma through 250 w . since these resistance values are so close, 249 w is chosen as the resistor across which the receiver is connected, and no other series resistance is needed in the transmit path, as figure 37 illustrates. t7250c: ideally, the transmitter should be driving into 425 w , and the t7256 receiver wants to see the levels that would result if the transmitter drove 6 ma through 312.5 w . so, the total transmit path resistance should be divided into three resistors. the ?st is the resistor across which the receiver is con- nected and should be approximately 312.5 w so that the receiver sees the correct levels. a standard 309 w value is adequate for this case. the remainder of the 425 w should be divided equally between two other series resistors in the transmit path, and (425 ? 309)/2 is 58.0 w , so a standard 57.6 w value is chosen for the two other series resistors as illustrated in figure 38. d) receiver bias: normally, the transmitter of the t7903/ t7250c is biased at 5 v through 100 k w pull- up, and the receiver of the t7256 is biased at 2.16 v through a resistor network that can be simpli?d as shown in figure 33 (a). when the direct-connect scheme is implemented, the resulting network between the t7903/ t7250c transmitter and the t7256 receiver is as shown in figure 33 (b). (a) (b) 5-4726 figure 33. receiver bias note that the receiver bias in figure 33 (b) is increased to 2.33 v (from 2.16 v in figure 33 (a)). this is an increase of about 8% (0.67 db). this will decrease the overall receiver sensitivity slightly. normally, the receiver must have a sensi- tivity to signals down to ?.5 db of nominal. therefore, in the case of a direct connect, the sensitivity is not an issue since the receiver will always see a large input signal. 5 v 5 v 5 v chip pin 100 k w 30 k w 23 k w 2.16 v chip pin 10 k w 100 k w chip pin 30 k w 23 k w 2.33 v 100 k w
data sheet january 1998 t7256 single-chip nt1 (scnt1) transceiver lucent technologies inc. 91 questions and answers (continued) s/t-interface (continued) a36: (continued) t7256 transmit to t7903/t7250c receive a) transmitter load: the t7256 s/t line interface transformer has a turns ratio of 2.5, and the transmitter drives a line-side load of 50 w . re?cting this imped- ance to the device side of the transformer results in 312.5 w (50 w x n 2 ). this resis- tance, combined with the 242 w total resis- tance of the device-side resistors, results in a total of 554.5 w that the transmitter typically drives. so, to optimize the transmitter part of the circuit based on the load the transmitter expects to drive, the transmitter should see a total resistance of approximately 554.5 w . b) receiver levels: t7903: the s/t line interface transformer has a turns ratio of 2.0. the receiver expects to see nominal pulse levels of 750 mv x 2.0 = 1.5 v. the t7256 transmitter circuit is a cur- rent source of 6.0 ma. to generate a voltage of 1.5 v with 6.0 ma requires a resistance of 1.5/0.006 = 250 w . t7250c: the s/t line interface transformer has a turns ratio of 2.5. the receiver expects to see nominal pulse levels of 750 mv x 2.5 = 1.875 v. the t7256 transmitter circuit is a cur- rent source of 6.0 ma. to generate a voltage of 1.875 v with 6.0 ma requires a resistance of 1.875/0.006 = 312.5 w . c) resistor selection: in this section, the term receiver implies not only the receive section on the chip, but also the external 10 k w resistors connected to the receiver. these resistors remain unchanged from the standard line interface circuit in order to maintain the same total receiver imped- ance. t7903: ideally, the t7256 transmitter should be driving into 554.5 w , and the t7903 receiver wants to see the levels that would result if the transmitter drove 6 ma through 250 w . so, the total transmit path resistance should be divided into three resistors. the ?st is the resistor across which the receiver is connected and should be approximately 250 w so that the receiver sees the correct levels. a standard 249 w value is adequate for this case. the remainder of the 554.5 w should be divided equally between two other series resistors in the transmit path, and (554.5 w ?249 w )/2 is 152.7 w , so 150 w is chosen for the two other series resistors as illustrated in figure 37. t7250c: ideally, the t7256 transmitter should be driving into 554.5 w , and the t7250c receiver wants to see the levels which would result if the transmitter drove 6 ma through 312.5 w . so, the total transmit path resistance should be divided into three resistors. the ?st is the resistor across which the receiver is connected and should be approximately 312.5 w so that the receiver sees the correct levels. a standard 309 w value is adequate for this case. the remainder of the 554.5 w should be divided equally between two other series resistors in the transmit path, and (554.5 w ?309 w )/2 is 122.6 w , so 121 w is chosen for the two other series resistors as illustrated in figure 38. d) receiver bias: the receiver bias is not an issue for the same reasons discussed in the t7903/t7250c transmit to t7256 receive section.
data sheet t7256 single-chip nt1 (scnt1) transceiver january 1998 92 lucent technologies inc. questions and answers (continued) s/t-interface (continued) a36: (continued) t7903/t7250c to t7256 direct connect with external s/t-interface provided first, we need to address the issue of the trans- former turns ratio. t7903: the t7903 uses a 2.0:1 transformer, and the t7256 uses a 2.5:1 transformer. it is desirable to be able to use a dual transformer, so we want the transmit- and receive-side transformers to have the same turns ratio. also, it may be desir- able to use a product with this arrangement as just a te (with an external nt1, i.e., no u-inter- face connected to the integrated nt1). therefore, we will select a 2.0:1 turns ratio transformer to ensure t7903 pulses of suf?ient amplitude on the line side of the transformer and ensure that an external transmitter won? overdrive the t7903 receiver inputs. t7250c: the t7250c and t7256 both use a 2.5:1 transformer, which simpli?s the analysis for this case. t7903/t7250c transmit to t7256 receive a) transmitter load: if we use the same s/t transmitter line inter- face circuit as in the normal (stand-alone te) case, the transmitter will see the load that it expects to drive and is thus optimized in terms of the load. the 100 w terminations must be user selected per the following table: b) receiver levels: the t7256 s/t line interface transformer has a turns ratio of 2.5. the t7256 receiver thus expects to see nominal pulse levels of 750 mv x 2.5 = 1.875 v at the device side of the trans- former. t7903: the t7903 transmitter (or an external te on a 0-length loop) will drive 750 mv pulses on the s/t line, and that voltage re?cted back to the device side of the trans- former is 750 mv x 2.0 = 1.5 v. if the t7256 receiver is connected to the device side of the transformer as shown in figure 39, it will see 1.5 v instead of 1.875 v when a 750 mv pulse is present on the line. thus, there is an inherent pulse attenuation in this scheme of 1.9 db at the t7256 receiver. we need to be sure that the receiver will have adequate sensitivity to detect pulses from an external te that is some distance away. refer- ring to itu i.430, this circuit can only be used in a short passive bus (spb) mode when using the onboard nt1, because there is a local te (the t7903), so any external te that is also used will result in a passive bus con?- uration. itu-t i.430 states that the maximum attenuation in spb con?uration is 3.5 db. combining this with the inherent 1.9 db atten- uation results in a total possible signal attenu- ation of 5.4 db. the receiver must have a sensitivity of at least 7.5 db per itu-t i.430 section 8.6.2.3, so 5.4 db attenuation will present no problem in this case. t7250c: the t7250c transmitter (or an exter- nal te on a 0-length loop) will drive 750 mv pulses on the s/t line, and that voltage re?cted back to the device side of the trans- former is 750 mv x 2.5 = 1.875 v. if thet7256 receiver is connected to the device side of the transformer as shown in figure 40, it will see the 1.875 v pulse level it expects when a 750 mv pulse is present on the line. c) receiver bias: in the t7903 to t7256 direct connect section we showed that the receiver is biased by about 0.67 db from nominal due to the direct connect of the t7903 to the t7256. assuming the receiver sensitivity decreases by this much and combining this with the maximum 5.4 db attenuation found in the previous sec- tion results in a total of 6.07 db of required sensitivity, which is still within the 7.5 db requirement on the receiver. con?uration jmp1 jmp2 integrated nt1 used as nt1 (no external nt1 connected) no external te connected installed installed unterminated external te connected installed installed terminated (100 w ) external te connected installed not installed
data sheet january 1998 t7256 single-chip nt1 (scnt1) transceiver lucent technologies inc. 93 questions and answers (continued) s/t-interface (continued) a36: (continued) t7256 transmit to t7903/t7250c receive a) transmitter load: the t7256 s/t line interface transformer nor- mally has a turns ratio of 2.5, and the trans- mitter drives a line-side load of 50 w . re?cting this impedance to the device side of the transformer results in 312.5 w (50 w x n 2 ). this resistance, combined with the 242 w total resistance of the device-side resistors, results in a total of 554.5 w that the transmitter typically drives. so, to optimize the transmitter part of the circuit based on the load the trans- mitter expects to drive, the transmitter should see a total resistance of approximately 554.5 w . t7903: in this case, the t7256 transmitter is driving into a transformer with a turns ratio of 2.0. the pulse amplitude that the transmitter must generate on the device side of the trans- former is 1.5 v (resulting in a 750 mv pulse on the line in accordance with the standards). the t7256 transmitter circuit is a current source of 6.0 ma. to generate a voltage of 1.5 v with 6.0 ma requires a resistance of 1.5/ 0.006 = 250 w , which is 62.5 w when re?cted to the device side of the transformer. this impedance should consist of jumper-select- able 100 w and 167 w resistors as illustrated in figure 39. the table below lists the jumper settings for each possible con?uration. the total impedance the t7256 must drive (from the ?st paragraph of this section) is 554.5 w , and the impedance across the transformer leads is 250 w (from the second paragraph). the remaining 554.5 w ?250 w = 304.5 w is divided equally between the posi- tive and negative transmitter outputs, requir- ing 152 w in each leg. we can accomplish this with a 143 w resistor on the device side of the diode bridge and a 10 w resistor on the line side of the bridge. the resistance is split in this way to provide 10 w of current limiting through the diode bridge when the bridge is conducting (similar to the t7903 transmitter circuit). t7250c: referring to figure 40, if we use the same t7256 s/t transmitter line interface circuit as in the normal (stand-alone nt) case, the t7256 transmitter will see the 554.5 w load that it normally expects to drive and is thus optimized in terms of the load. the 100 w terminations shown are user selected per the preceding table. b) receiver levels: the t7903 will see the correct pulse levels by design. in the preceding section, the t7256 transmit circuit was designed to produce 750 mv pulses on the line. the t7903 receiver is attached directly to the device side of the transformer, so it will see the 1.5 v pulse levels that it expects to see. t7903: the t7903 s/t line interface trans- former has a turns ratio of 2.0. the t7903 receiver thus expects to see nominal pulse levels of 750 mv x 2.0 = 1.5 v at the device side of the transformer. the t7256 transmitter section was designed to produce 750 mv pulses on the s/t line (as would an external te on a 0-length loop). that voltage re?cted back to the device side of the t7901 trans- former is 750 mv x 2.0 = 1.5 v, so the t7901 sees the pulse level it expects when a 750 mv pulse is present on the line. t7250c: the t7250c s/t line interface trans- former has a turns ratio of 2.5. the t7250c receiver thus expects to see nominal pulse levels of 750 mv x 2.5 = 1.875 v at the device side of the transformer. the t7256 transmitter section was designed to produce 750 mv pulses on the s/t line (as would an external te on a 0-length loop). that voltage re?cted back to the device side of the t7250c trans- former is 750 mv x 2.5 = 1.875 v, so the t7250c see the pulse level it expects when a 750 mv pulse is present on the line. c) receiver bias: the receiver bias is suf?iently small that it is not an issue (see preceding sections). con?uration jmp3 jmp4 integrated nt1 used as nt1 (no external nt1 connected) no external te connected installed installed unterminated external te connected installed installed terminated (100 w ) external te connected installed not installed
data sheet t7256 single-chip nt1 (scnt1) transceiver january 1998 94 lucent technologies inc. questions and answers (continued) s/t-interface (continued) a36: (continued) 5-4721 figure 34. t7256 s/t line interface scheme 5-4722 * refer to the t7903 data sheet, figure f-10 for an example of a switch circuit that can be used here. figure 35. t7903 s/t line interface scheme tpr zd1 tnr t1 2.5:1 100 w 100 w jmp1 2 1 3 5 7 8 6 4 rj-45 rpr zd2 rnr 100 w jmp2 75 w 46.4 w 75 w 46.4 w 10 k w 46.4 w 10 k w 46.4 w d1 d3 d4 d2 d5 d7 d8 d6 100 w 6.8 v d9 d10 6.8 v c1 0.1 m f t2 2.5:1 t3 t7256 npx_pt zd1 npx_nt t1 2.0:1 100 w jmp1 t3 2 1 3 5 7 8 6 4 rj-45 npx_pr zd2 npx_nr 100 w jmp2 10 w 5 w 10 w 5 w 10 k w 10 w 10 k w 10 w d1 d3 d4 d2 d5 d7 d8 d6 6.8 v 6.8 v c1 0.1 m f t2 2.0:1 t7903 *
data sheet january 1998 t7256 single-chip nt1 (scnt1) transceiver lucent technologies inc. 95 questions and answers (continued) s/t-interface (continued) a36: (continued) 5-4723 * refer to the t7250 data sheet, figure f-10 for an example of a switch circuit that can be used here. figure 36. t7250c s/t line interface scheme note: the circuit shown above has subtle differences from that shown in the t7250c data sheet. either circuit is suitable, since they will both pass the required conformance tests. tpr zd1 tnr t1 2.5:1 100 w jmp1 t3 2 1 3 5 7 8 6 4 rj-45 rpr zd2 rnr 100 w jmp2 10 w 46.5 w 10 w 46.5 w 10 k w 46.5 w 10 k w 46.5 w d1 d3 d4 d2 d5 d7 d8 d6 6.8 v 6.8 v c1 0.1 m f t2 2.5:1 t7250c * d9 d10
data sheet t7256 single-chip nt1 (scnt1) transceiver january 1998 96 lucent technologies inc. questions and answers (continued) s/t-interface (continued) a36: (continued) 5-4724 figure 37. t7903 to t7256 direct-connect scheme 5-4725 figure 38. t7250c to t7256 direct-connect scheme rnr rpr tnr tpr npx_pt npx_nt npx_pr npx_pt 10 k w 10 k w 249 w 10 k w 150 w 150 w 249 w 10 k w t7903 t7256 rnr rpr tnr tpr tpr tnr rpr rnr 10 k w 10 k w 309 w 10 k w 121 w 121 w 309 w 10 k w t7250c t7256 57.6 w 57.6 w
data sheet january 1998 t7256 single-chip nt1 (scnt1) transceiver lucent technologies inc. 97 questions and answers (continued) s/t-interface (continued) a36: (continued) 5-4728 * refer to the t7903 data sheet, figure f-10 for an example of a switch circuit that can be used here. figure 39. t7903 to t7256 direct-connect scheme with external s/t-interface zd1 t1 2.0:1 100 w 100 w jmp1 t3 2 1 3 5 7 8 6 4 rj-45 zd2 167 w jmp3 10 w 5 w 10 w 5 w 143 w 10 w 143 w 10 w d1 d3 d4 d2 d5 d7 d8 d6 100 w 6.8 v 6.8 v 0.1 m f t2 2.0:1 jmp2 jmp4 t7256 t7903 rpr rnr t7903 t7256 npx_pt npx_nt tpr tnr 10 k w 10 k w 10 k w 10 k w npx_pr npx_nr *
data sheet t7256 single-chip nt1 (scnt1) transceiver january 1998 98 lucent technologies inc. questions and answers (continued) s/t-interface (continued) a36: (continued) 5-4727 * refer to the t7250 data sheet, figure f-10 for an example of a switch circuit that can be used here. figure 40. t7250c to t7256 direct-connect scheme with external s/t-interface zd1 t1 2.5:1 100 w 100 w jmp1 t3 2 1 3 5 7 8 6 4 rj-45 zd2 100 w jmp3 10 w 46.5 w 10 w 46.5 w 75 w 46.5 w 75 w 46.5 w d1 d3 d4 d2 d5 d7 d8 d6 100 w 6.8 v d9 d10 6.8 v 0.1 m f t2 2.5:1 jmp2 jmp4 t7256 t7250c rpr rnr rpr rnr t7250c t7256 tpr tnr tpr tnr 10 k w 10 k w 10 k w 10 k w *
data sheet january 1998 t7256 single-chip nt1 (scnt1) transceiver lucent technologies inc. 99 questions and answers (continued) s/t-interface (continued) q37: what is the state of the d-echo bit during an eoc 2b+d loopback? a37: the d-echo bit (sxe, gr2, bit 3) should be set to zero to meet the itu-t i.430 requirement in appendix i, note 4, which states that during a loopback 2 (eoc 2b+d loopback), the nt1 should send info 4 frames toward the te with the d- echo channel bits set binary zero. if autoeoc = 1 (register gro, bit 4), sxe is internally overrid- den to 0 by the t7256. if autoeoc = 0, sxe must be set to 0 by the user. q38: is it possible to make a nontransparent single b- channel loopback toward the s/t-interface via the microprocessor? a38: yes. refer to the data sheet for a description of the itu-t i.430 loop c loopback control bits (reg- ister dfro). q39: what is the purpose of the sfecv bit in register sir0? a39: ansi t1 t1.605 table 6, ?odes for q-channel and sc1-subchannel messages, de?es an sc1-subchannel message, ?ar-end code viola- tion (sc11, sc12, sc13, sc14 = 1110). this is an s-channel message that the nt can send to the te to indicate that a previous multiframe received by the nt contains one or more illegal s/t line code violations. in an nt1 that supports multiframing, the sfecv bit can be used to gen- erate an interrupt to the t7256 microprocessor indicating that it should transmit the ?ar-end code violation message to the te in s-subchan- nel one. this subchannel is accessed via register mcr1 bits 0?. q40: in the analog interface section of the s/t-inter- face description in the data sheet, where does the value of 0 ms?.1 ms maximum differential delay in adaptive timing mode come from? a40: the minimum value of 0 ms is necessary so that the nt's transmitter and receiver can be directly connected in a loopback and still synchronize. the maximum value of 3.1 ms comes about because the window size needed in the adaptive timing algorithm is 2.1 ms. the window size is the time during each bit period in which no transitions may occur. since a period is 5.2 ms, the time dur- ing which there may be transitions is 5.2 ms ?2.1 ms, or 3.1 ms. this is the same as the maximum differential delay, since the earliest and latest bit transitions represent the nearest and farthest tes relative to the nt receiver. miscellaneous q41: is the 100 ppm free-run frequency recommen- dation met in the t7256? a41: in the free-run mode, the output frequency is pri- marily dependent on the crystal, not the silicon design. for low-cost crystals, initial tolerance, temperature, and aging effects may account for two-thirds of this budget, and just a couple of pf of variation in load capacitance will use up the rest; therefore, the 100 ppm goal can be met if the crystal parameters are well controlled. see the crystal characteristics section in this data sheet. q42: what happens if co and cm of the crystal differs from the speci?ation shown in the crystal char- acteristics table? a42: none of the parameters should be varied. we have not characterized any such crystals, and have no easy method of doing so. a crystal whose parameters deviate from the requirements may work in most applications but fail in isolated cases involving certain loop con?urations or other system variations. therefore, customers choosing to vary any of these parameters do so at their own risk. q43: it has been noted in some other designs that the crystal has a capacitor from each pin to ground. changing these capacitances allows the fre- quency to be adjusted to compensate for board parasitics. can this be done with the t7256 crys- tal? also, can we use a crystal from our own manufacturer? a43: for the t7256, these capacitors are located on the chip, so their values are ?ed. the advantage to this is that no external components are required. the disadvantage is that board parasit- ics must be very small.
data sheet t7256 single-chip nt1 (scnt1) transceiver january 1998 100 lucent technologies inc. questions and answers (continued) miscellaneous (continued) a43: (continued) the crystal characteristics section of the data sheet notes that the board parasitics must be within the range of 0.6 pf 0.4 pf. q44: what clocks are available on the t7256? a44: the following clocks are available and are always present once enabled, regardless of the state of activation on the u- or s/t-interfaces: 1. syn8k, pin 4 (8 khz clock) is enabled by hold- ing sdi (pin 12) low during an external reset . 2. tdmclk, pin 9 (2.048 mhz clock) is enabled by writing tdmen = 0 (register gr2, bit 5). 3. ckout, pin 17 (10.24 mhz or 15.36 mhz clock) is enabled by writing register gro bit 2 or 1, respectively, to 0. normally 3-stated. note that using clocks 2 or 3 above requires a microprocessor for setting the appropriate con?- uration. q45: i plan to program the t7256 to output 15.36 mhz from its ckout pin. is this clock a buffered version of the 15.36 mhz oscillator clock? i am concerned that if it is not buffered, the capacitive loading on this pin could affect the sys- tem clock frequency. a45: the 15.36 mhz output is a buffered version of the xtal clock and therefore hanging capacitance on it will not affect the t7256s system clock fre- quency. q46: how does the ?tering at the optoin input work? a46: the signals applied to optoin are digitally ?- tered for 20 ms. any transitions under 20 ms will be ignored. q47: what is the isolation voltage of the 6n139 optoisolator used in the dc termination circuit of the t7256? a47: 2500 vac, 1 minute. q48: can the t7256 operate with an external 15.36 mhz clock source instead of using a crys- tal? a48: yes, by leaving x1 disconnected and driving x2 with an external cmos-level oscillator. q49: what is the effect of ramping down the power- supply voltage on the device? when will it provide a valid reset? this condition can occur when a line-powered nt1s line cord is repeatedly plugged in and removed and plugged in again before the power supply has had enough time to fully ramp-up. a49: the devices reset is more dependent on the reset pin than the power supply to the device. as long as the proper input conditions on the reset pin (see table 42) are met, the device will have a valid reset. note that this input is a schmitt-trigger input. q50: is there a recommended method for powering the t7256? for example, is it desirable to separate the power supplies, etc.? a50: the t7256 is not extremely sensitive to power- supply schemes. following standard practices of decoupling power supplies close to the chip and, if power and ground planes are not used, keeping power traces away from high-frequency signals, etc., should yield acceptable results. separating the t7256 analog power supplies from the digital power supplies near the chip may yield a small improvement, and the same holds true for using power and ground planes vs. discrete traces. note that if analog and digital power supplies are separated, the crystal power supply (v ddo ) should be tied to the digital supplies (v ddd ). see the scnti family reference design board hardware user manual (mn96-011isdn), appendix a for an example of a board layout that performs well. q51: what are the ?ter characteristics of the pll at the nt? a51: the ? db frequency is approximately 5 hz, peaking is about 1.2 db. q52: can the t7256 operate in the lt mode? a52: no, the t7256 is optimized for the nt side of the loop and cannot operate in the lt mode.
data sheet january 1998 t7256 single-chip nt1 (scnt1) transceiver lucent technologies inc. 101 questions and answers (continued) miscellaneous (continued) q53: can you provide detailed information on the active and idle power consumption of the t7256? a53: the idle power of the t7256 is typically 35 mw. the idle power will be increased if ckout or the tdm highway are active. the discussion below presents accurate numbers for adding in the effects of ckout and the tdm highway. when considering active power measurement ?- ures, it is important to note that the conditions under which power measurements are made are not always completely stated by 2b1q ic ven- dors. for example, loop length is not typically mentioned in the context of power dissipation, yet power dissipation on a short loop is noticeably greater than on a long loop. there are two rea- sons for the increased power dissipation at shorter loop lengths: 1. the overall loop impedance is smaller, requir- ing a higher current to drive the loop. 2. the far-end transceiver is closer, requiring the near-end transceiver to sink more far-end cur- rent in order to maintain a virtual ground at its transmitter outputs. the following lab measurements provide an example of how power dissipation varies with loop length for a speci? t7256 with its 15.36 mhz ckout output disabled (see the fol- lowing table for information on ckout). note that power dissipation on a 0-length loop (the worst- case loop) is about 35 mw higher than on a loop of >3 kft length? signi?ant difference. thus, loop length needs to be considered when deter- mining worst-case power numbers. table 43. power dissipation variation * this is the con?uration used by some ic manufacturers. also, in the case of the t7256, the use of the out- put clock ckout (pin 17) needs to be considered since its in?ence on power dissipation is signi? cant. some applications may make use of this clock, while others may leave it 3-stated. the power dissipation of ckout is shown in table 44. table 44. power dissipation of ckout another factor in?encing power consumption is the s/t-interface data pattern. for example, when transmitting an info 4 pattern with all 1s data in the b and d channels, the power consumption is 25 mw lower than it is when transmitting info 2, because info 2 is worst case in terms of the amount of +0 and ? transitions, and info 4 is best case if the data is all 1s. a typical number would lie about midway between these two. the t7256 tdm highway, when active, can add another 3 mw of power. loop configuration power (mw) 18 kft/26 awg 270 6 kft/26 awg 270 3 kft/26 awg 274 2 kft/26 awg 277 1 kft/26 awg 285 0.5 kft/26 awg 293 0 kft 305 135 w load, iloss or lpbk active, no far-end transceiver* 278 ckout frequency (mhz) power due to ckout 40 pf load (mw) power due to ckout no load (mw) 15.36 21.3 11.0 10.24 17.7 9.1
data sheet t7256 single-chip nt1 (scnt1) transceiver january 1998 102 lucent technologies inc. questions and answers (continued) miscellaneous (continued) a53: (continued) therefore, it is apparent that the conditions under which power is measured must be clearly speci?d. the methods lucent has used to evaluate typical and worst-case power consumption are based on our commit- ment to provide our customers with accurate and reliable data. measurements are performed as part of the factory test procedure using automated test equipment. bench top tests are performed in actual t7256- based systems to correlate the automated test data with an actual implementation. a conservative margin is then added to the test results for publication in our data sheets. the following table provides power-consumption data for several scenarios so that knowledgeable customers can fairly compare transceiver solutions. a baseline scenario is presented in the case 1 column, and then adders are listed in the cases 2? columns to account for the worst-case condition listed in each column so that an accurate worst-case ?ure can be determined based on the conditions that are present in a particular application. note that the tests were run at 5 v, so changes in the supply voltage will change the power accordingly. table 45. power consumption * some 2b1q silicon vendors specify power using a configuration in which the ic is active and transmitting into a 135 w termination, with no far-end transmitter attached. this configuration would cause an increase of 9 mw over the case 1 column, instead of the 35 mw shown here. this highlights the importance of specifying measurement conditions accurately when making comparisons between chip vendors' power numbers. ? this is a worst-case number representing the state of the s/t-interface where the most +0/? transitions occur. in a real application, this will be a transient state, as info 4 will occur as soon as synchronization is achieved. the average power consumed during a typ- ical info 4, assuming a 50% mix of 1s and 0s in the b and d channels, would be approximately half this number, or 13 mw. ? see the preceding table for a comparison of power dissipation with negligible capacitive loading on ckout. the 40 pf figure chosen here is intended to represent a worst-case condition. q54: what would cause the stled indicator to ?sh sporadically at an 11 hz rate? a54: if the t7256 s/t-interface is operating over a long loop that is outside the range speci?d in the i.430/t1.605 standard, the t7256 may go into a state where it is constantly going in and out of synchronization. this causes it to cycle between ansi states h7 and h8, producing stled state changes between 1 hz ?shing and always on. when the s/t-interface loses synchronization, it takes about 96 ms before synchronization can be reacquired. this 96 ms cycle, coupled with the stled switching from always on to 1 hz ?shing, can appear as 11 hz or sporadic ?shing, depending on how frequently s/t synchronization is being lost. variables baseline adders case 1 case 2 case 3 case 4 case 5 case 6 loop configuration >3 kft, 26 awg 0 kft* s/t state info 4 with all 1s data info 2 ? ckout, mhz (40 pf load) 3-stated 15.36 temperature ( c) 25 85 tdm highway inactive active typical power consumption (mw) 254 35 26 22 5 3
data sheet january 1998 t7256 single-chip nt1 (scnt1) transceiver lucent technologies inc. 103 questions and answers (continued) miscellaneous (continued) a54: (continued) either of these states could cause potential con- fusion to maintenance personnel in the event that a t7256-based nt1 is connected to an s/t loop that is longer than permitted by the standards. for example, an 11 hz rate is dif?ult to visually distinguish from the 8 hz rate, but the 11 hz case indicates a problem on the s/t-interface and the 8 hz case indicates a problem on the u-interface. to troubleshoot the stled indication, unplug the s/t connector and repower the t7256 and initiate a start-up on the u-interface. if there is no prob- lem on the u-interface, the stled will reach a 1 hz ?shing state and remain there, indicating that the fast ?shing was a result of s/t-interface problems. q55: the stled on my t7256-based nt1 behaves in an unexpected way. when a start-up attempt is received, it ?shes at an 8 hz rate. then it ?shes brie? at 1 hz, indicating synchronization on the u-interface. this is expected. however, after this, it starts ?shing at 8 hz, and yet it appears as though the system is operating ?e (data is being passed end to end, etc.). shouldn? the stled signal be always low (i.e., on) at this point? a55: yes it should. referring to the stled control flow diagram in figure 18 of this data sheet, it appears as though you may be receiving aib = 0 from the upstream u-interface element. this will cause the behavior you are seeing. if you have access to the microprocessor registers, you can check this by monitoring register cfr1, bit 6 to see if it ever goes to 0. q56: we have equipment that operates ?e against a 5ess?switch, but never gets to layer 3 when operating against a northern telecom dms-100 switch. the equipment uses the scnt1 device talking to a motorola mc68360 device over the tdm highway and serial m p port. we do not use the s/t-interface connection on the scnt1 instead we originate and terminate the calls on the scnt1 tdm highway. do you have any idea what the problem may be? a56: some dms-100 switches require that the upstream u-overhead bit sai (s/t-interface activ- ity indicator) is set to 1 before they allow full transparency at layer 3. the state of the transmit- ted sai bit in the scnt1 is controlled by register gr1, bits 7 & 8. the default state of these bits causes transmission of an sai that re?cts the s/t-interface status. since there is no te con- nected in this particular product, sai = 0 is trans- mitted upstream to the switch by default. to override this value and force sai to 1 (which is necessary for transparency in this case), bit 7, 6 should be set to 0, 1, respectively. note that the switch software in this case is not in accordance with ansi t1.601-1992. q57: we are testing out t7256-based equipment against a lucent slc series 5, and performance seems ok except that we get a burst of errors, and even drop calls, approximately every 15 min- utes. can you explain why? a57: check to make sure that your equipment is set- ting the ps1/ps2 power status bits correctly. the slc equipment monitors the ps1/2 bits and, if they are both zero (meaning all power is lost), it assumes that there is some sort of terminal error, since this is not an appropriate steady-state value for ps1/2. when this condition is detected, the slc deactivates and reactivates the line approxi- mately every 15 minutes. this causes the symp- toms you describe. q58: when i try to activate our t7256-based nt1, it appears as though the u-interface is synchroniz- ing (i.e., stled ?shes at 1 hz), but the s/t-interface won? activate, and there is not even any signal activity on the s/t-interface (i.e., no info 1 or info 2). what might the problem be? a58: the behavior you have observed can be caused if the uoa bit received on the u-interface from the network is set to 0. this causes the t7256 to acti- vate the u-interface only, keeping the s/t-interface quiet, per the ansi and etsi stan- dards. we have heard of some network equip- ment that incorrectly sets this bit low. if you have access to the microprocessor registers, you can check this by monitoring register cfr1 bit 3 to see if it is low. if it is, the problem is in the network equipment, not your nt1.
data sheet t7256 single-chip nt1 (scnt1) transceiver january 1998 104 lucent technologies inc. questions and answers (continued) miscellaneous (continued) q59: what is the state of the t7256 tdm bus output when the unused bits of the d-channel octet are transmitted? a59: the t7256 3-states the tdm bus output when b- and d-channel information is not transmitted to the tdm bus. this includes the 6-bit interval in the d-channel octet. q60: what is the purpose of the actsel bit in register gr2 bit 6? a60: this bit is to provide compatibility with the ansi t1.601 and etsi etr 080 standards. the 1992 version of t1.601 (the most recent as of this writ- ing) speci?s that, upon a loopback 2 eoc request, the nt1s 2b+d data should be looped back immediately and the upstream (nt-to-lt) act bit should be set to 0. ansi speci?d that the upstream act bit should be set to 0 to indicate to the lt that end-to-end data transparency (te-to- lt) is interrupted during a loopback 2. the fact that 2b+d data is looped back immediately means that upstream data transparency at the nt is established independent of the status of the act bit from the lt. normally, upstream data transparency at the nt is dependent on act = 1 being received from the lt. the reason that loop- back 2 transparency criteria differ is that there is no guarantee that the nt1 will receive act = 1 from the lt. consider the case where an lt wants to activate the u-interface and perform a loopback 2 test on an nt1 with no te con- nected. in this case, the lt will never receive act = 1 since, prior to the loopback 2 request, act = 0 because there is no te attached, and after the loopback 2 request, act = 0 because layer 1 transparency is interrupted. since the lt will never receive act = 1 from the nt1, it will never send act = 1 back to the nt1. since the nt1 receipt of act = 1 normally enables upstream transparency, ansi chose to make an exception to the data transparency requirements in this case and enable upstream transparency immedi- ately upon receipt of the loopback 2 eoc com- mand at the nt1. the major difference between the ansi and etsi standards with regard to how the nt1 handles a loopback 2 request lies in what happens to the upstream act bit. ansis position is that act should be set to 0 because a loopback 2 is an interruption to layer 1 transparency. etsis posi- tion is that the state of the act bit should only be dependent on whether or not the nt1 is receiving info 3 from the te (this is consistent with ansi t1.601 paragraph 6.4.6.4 and etsi etr 080 paragraph a.10.1.5.1). during a loopback 2, the t7256 will always receive info 3 at the s/t-inter- face (even if there is no te attached) because it loops back its s/t transmit signal and synchro- nizes itself to that signal. therefore, the possibility that lt will never receive act = 1 from the nt does not exist under these rules. as a result, no special exceptions need to be applied to the case of loopback 2 in etsi. for example, again con- sider the case where an lt wants to activate the u-interface and perform a loopback 2 test on an nt1 with no te connected. the nt1 will synchro- nize to its own s/t signal and detect info 3. this will cause act = 1 to be transmitted upstream. the lt will detect act = 1 and set its downstream act = 1. when the nt detects the downstream act = 1, it will enable upstream data transparency. the handling of the act bit and transparency in this case is the same as for a normal activation. in the etsi standard, transparency at the nt dur- ing loopback 2 is dependent upon the reception of the act bit from the lt, i.e., if act = 1, loopback transparency is established, and if act = 0, loop- back data is forced to all 1s. the lt won? send act = 1 until it receives act = 1 from the nt. the nt will not send act = 1 to the lt until it receives an info 3 indication (i.e., until its s/t-interface is synchronized as described in the register gr2 actsel bit de?ition). thus, data transparency requires that the nt1 set its upstream act bit to 1. there is a contribution that has been voted onto the ansi t1e1.4 living list that changes the act bit behavior during loopback 2 to match that speci?d for etsi (contribution #t1e1.4/92-089). thus, the next issue of the t1.601 standard will bring the ansi and etsi standards into harmony as pertains to handling of the act bit during a loopback 2.
data sheet january 1998 t7256 single-chip nt1 (scnt1) transceiver lucent technologies inc. 105 glossary actmode/int : act bit mode, serial interface microprocessor interrupt. actr: receive activation (register cfr1, bit 0). actsc: activation/deactivation state change on u-interface (register uir0, bit 1). actscm: activation/deactivation state change on u-interface interrupt mask (register uir1, bit 1). actsel: act mode select (register gr2, bit 6). actt: transmit activation (register gr1, bit 4). afrst: adaptive filter reset (register cfr0, bit 1). aib: alarm indication bit (register cfr1, bit 6). ansi: american national standards in- stitute. asi: alternate space inversion. autoact: automatic activation control (register gr0, bit 6). autoctl: auto control enable (register gr0, bit 3). autoeoc: automatic eoc processor enable (register gr0, bit 4). a[3:1]r: receive eoc address (register ecr2, bits 0?). a[3:1]t: transmit eoc address (register ecr0, bits 0?). berr: block error on u-interface (register uir0, bit 2). berrm: block error on u-interface inter- rupt mask (register uir1, bit 2). ccrc: corrupt cyclic redundancy check (register ecr0, bit 7). cdm: charged-device model. cfr0: control flow state machine con- trol?aintenance/reserved bits register. cfr1: control flow state machine status register. cfr2: control flow state machine status?eserved bits register. ckout: clock output. codec: coder/decoder, typically used for analog-to-digital conversions or digital-to-analog conversions. crate[1:0]: ckout rate control (register gr0, bits 2?). crc: cyclic redundancy check. dfr0: data flow control? and s/t b-channels register. dfr1: data flow control?-channels and tdm bus register. dmr: receive eoc data or message in- dicator (register ecr2, bit 3). dmt: transmit eoc data or message in- dicator (register ecr0, bit 3). dpgs: digital pair gain system. ecr0: eoc state machine control?d- dress register. ecr2: eoc state machine status?d- dress register. ecr3: eoc state machine status?nfor- mation register. emint: exit maintenance mode interrupt (register mir0, bit 2). emintm: exit maintenance mode interrupt mask (register mir1, bit 2). eoc: embedded operations channel. eocsc: eoc state change on u-interface (register uir0, bit 0). eocscm: eoc state change on u-interface mask (register uir1, bit 0).
data sheet t7256 single-chip nt1 (scnt1) transceiver january 1998 106 lucent technologies inc. glossary (continued) erc1: eoc state machine control information register. esd: electrostatic discharge. etsi: european telecommunications standards institute. febe: far-end block error (register cfr1, bit 5). fsc[2:0]: frame strobe (fs) control, (register tdr0, bits 2?). fsp: frame strobe (fs) polarity (register tdr0, bit 3). ft: fixed/adaptive timing control (register gr2, bit 0). fte/tdmdi: fixed/adaptive timing mode select. gir0: global interrupt register. gnd a : analog ground. gnd o : crystal oscillator ground. gr0: global device control?evice configuration register. gr1: global device control u-interface register. gr2: global device control s/t-interface register. hbm: human-body model. hdlc: high-level data link control. highz : high impedance control. hn: hybrid negative input for u-interface. hp: hybrid positive input for u-interface. i4c: info 4 change (register sir0, bit 3). i4cm: info 4 change mask (register sir1, bit 3). i4i: info 4 indicator (register cfr1, bit 7). ilint: insertion loss interrupt (register mir0, bit 1). ilintm: insertion loss interrupt mask (register mir1, bit 1). iloss: insertion loss test control (register cfr0, bit 0). iloss : insertion loss test control. isdn: integrated services digital net- work. itu-t: international telecommunication union-telecommunication sec- tor. i[8:1]r: receive eoc information (register ecr3, bits 0?). i[8:1]t: transmit eoc information (register erc1, bits 0?). lon: line driver negative output for u-interface. lop: line driver positive output for u-interface. lpbk: u-interface analog loopback (register gr1, bit 0). mcr0: q-channel bits register. mcr1: s subchannel 1 register. mcr2: s subchannel 2 register. mcr3: s subchannel 3 register. mcr4: s subchannel 4 register. mcr5: s subchannel 5 register. mint: maintenance interrupt (register gir0, bit 2). mir0: maintenance interrupt register. mir1: maintenance interrupt mask register. mlt: metallic loop termination. multif: multiframing control (register gr0, bit 5). nebe: near-end block error (register cfr1, bit 4). ntm: nt test mode (register gr1, bit 3). oof: out of frame (register cfr1, bit 2). optoin: optoisolator input. ousc: other u-interface state change (register uir0, bit 3).
data sheet january 1998 t7256 single-chip nt1 (scnt1) transceiver lucent technologies inc. 107 glossary (continued) ouscm: other u-interface state change mask (register uir1, bit 3). ps1: power status #1 (register gr1, bit 2). ps1e/tdmdo: power status #1, tdm clock. ps2: power status #2 (register gr1, bit 1). ps2e/tdmclk: power status #2, tdm data out. qmint: quiet mode interrupt (register mir0, bit 0). qmintm: quiet mode interrupt mask (register mir1, bit 0). qsc: q-bits state change (register sir0, bit 1). qscm: q-bits state change mask (register sir1, bit 1). q[4:1]: q-channel bits (register mcr0, bits 0?). r25r: receive reserved bits (register cfr2, bit 2). r25t: transmit reserved bit (register cfr0, bit 4). r64t: transmit reserved bit (register cfr0, bit 5). reset : reset. rnr: receive negative rail for s/t-interface. rpr: receive positive rail for s/t-interface. rsfint: receive superframe interrupt (register uir0, bit 4). rsfintm: receive superframe interrupt mask (register uir1, bit 4). r[16:15]r: receive reserved bits (register cfr2, bits 1?). r[16:15]t: transmit reserved bits (register cfr0, bits 3?). r[64:54:44:34]r: receive reserved bits (register cfr2, bits 6?). sai[1:0]: s/t-interface activity indicator control (register gr1, bits 6?). sc1[4:1]: s subchannel 1 (register mcr1, bits 0?). sc2[4:1]: s subchannel 2 (register mcr2, bits 0?). sc3[4:1]: s subchannel 3 (register mcr3, bits 0?). sc4[4:1]: s subchannel 4 (register mcr4, bits 0?). sc5[4:1]: s subchannel 5 (register mcr5, bits 0?). sck: serial interface clock. sdi: serial interface data input. sdinn: sigma-delta a/d negative input for u-interface. sdinp: sigma-delta a/d positive input for u-interface. sdo: serial interface data output. sfecv: s-channel far-end code violation (register sir0, bit 2). sfecvm: s-subchannel far-end code viola- tion mask (register sir1, bit 2). sint: s/t-transceiver interrupt (register gir0, bit 1). sir0: s/t-interface interrupt register. sir1: s/t-interface interrupt mask register. som: start of multiframe (register sir0, bit 0). somm: start of multiframe mask (register sir1, bit 0). spwrud: s/t-interface powerdown control (register gr2, bit 1). sreset: s/t-interface reset (register gr2, bit 2). stled: status led driver. stoa: s/t-only activation (register gr2, bit 7). superframe: eight u-frames grouped together.
data sheet t7256 single-chip nt1 (scnt1) transceiver january 1998 108 lucent technologies inc. glossary (continued) sxb1[1:0]: s/t-interface transmit path source for b1 channel (register dfr0, bits 5?). sxb2[1:0]: s/t-interface transmit path source for b2 channel (register dfr0, bits 7?). sxd: s/t-interface transmit path source for d channel (register dfr1, bit 1). sxe: s/t-interface d-channel echo bit control (register gr2, bit 3). syn8k/lbind/fs: synchronous 8 khz clock or loop- back indicator, frame strobe. tdm: time-division multiplexed. tdmb1s: tdm bus transmit control for b1 channel from s/t-interface (register dfr1, bit 2). tdmb1u: tdm bus transmit control for b1 channel from u-interface (register dfr1, bit 5). tdmb2s: tdm bus transmit control for b2 channel from s/t-interface (register dfr1, bit 3). tdmb2u: tdm bus transmit control for b2 channel from u-interface (register dfr1, bit 6). tdmds: tdm bus transmit control for d channel from s/t-interface (register dfr1, bit 4). tdmdu: tdm bus transmit control for d channel from u-interface (register dfr1, bit 7). tdmen: tdm bus select (register gr2, bit 5). tdr0: tdm bus timing control register. tnr: transmit negative rail for s/t-interface. tpr: transmit positive rail for s/t-interface. tsfint: transmit superframe interrupt (register uir0, bit 5). tsfintm: transmit superframe interrupt mask (register uir1, bit 5). u frame: an 18-bit synchronous word. u2bdln: nontransparent 2b+d loopback control (register gr2, bit 4). u2bdlt: transparent 2b+d loopback con- trol (register ecr0, bit 6). ub1lp: u-interface loopback of b1 chan- nel control (register ecr0, bit 4). ub2lp: u-interface loopback of b2 chan- nel control (register ecr0, bit 5). uint: u-transceiver interrupt (register gir0, bit 0). uir0: u-interface interrupt register. uir1: u-interface interrupt mask register. uoa: u-interface only activation, (register cfr1, bit 3). uxb1[1:0]: u-interface transmit path source for b1 channel (register dfr0, bits 1?). uxb2[1:0]: u-interface transmit path source for b2 channel (register dfr0, bits 3?). uxd: u-interface transmit path source for d channel (register dfr1, bit 0). v dda: analog power. v ddo: crystal oscillator power. vrcm: common-mode voltage reference for u-interface circuits. vrn: negative voltage reference for u- interface circuits. vrp: positive voltage reference for u- interface circuits. x1: crystal #1. x2: crystal #2. xact: u-transceiver active (register cfr1, bit 1). xpcy: transparency (register gr1, bit 5).
data sheet january 1998 t7256 single-chip nt1 (scnt1) transceiver lucent technologies inc. 109 standards documentation telecommunication technical standards and reference documentation may be obtained from the following organizations: ansi (u.s.a.): american national standards institute (ansi) 11 west 42nd street new york, new york 10036 tel: 212-642-4900 fax: 212-302-1286 lucent technologies publications: lucent technologies customer information center (cic) tel: 800-432-6600 fax: 800-566-9568 (in u.s.a.) fax: 317-322-6484 (outside u.s.a.) bellcore (u.s.a.): bellcore customer service 8 corporate plaza piscataway, new jersey 08854 tel: 800-521-core (in u.s.a.) tel: 908-699-5800 fax: 212-302-1286 itu-t: international telecommunication union- telecommunication sector place des nations ch 1211 geneve 20, switzerland tel: 41-22-730-5285 fax: 41-22-730-5991 etsi: european telecommunications standards institute bp 152 f-06561 valbonne cedex, france tel: 33-92-94-42-00 fax: 33-93-65-47-16 ttc (japan): ttc standard publishing group of the telecommunications technology committee 2nd floor, hamamatsucho-suzuki building, 1 2-11, hamamatsu-cho, minato-ku, tokyo tel: 81-3-3432-1551 fax: 81-3-3432-1553
data sheet t7256 single-chip nt1 (scnt1) transceiver january 1998 110 lucent technologies inc. notes
data sheet january 1998 t7256 single-chip nt1 (scnt1) transceiver lucent technologies inc. 111 notes
for additional information, contact your microelectronics group account manager or the following: interne t : http://ww w .lucent.com/mic r o e-mail: docmaster@mic r o.lucent.com u . s .a.: microelectronics grou p , lucen t t echnologies inc., 555 union boul e v ard, room 30l-15p-ba, allent o wn, p a 18103 1-800-372-2447 , f ax 610-712-4106 (in cana d a : 1-800-553-2448 , f ax 610-712-4106) asia p a cific : microelectronics grou p , lucen t t echnologies singapore pt e . ltd., 77 science p a r k d r i v e , #03-18 cintech iii, singapore 118256 t el . (65) 778 8833 , f ax (65) 777 7495 j a p an: microelectronics grou p , lucen t t echnologies j apan ltd., 7-18, higashi-gotanda 2-chom e , shinag a w a-ku , t ok y o 141, j apan t el . (81) 3 5421 1600 , f ax (81) 3 5421 1700 eu r ope: data requests : mic r oelect r onics g r oup d a t aline : t el . (44) 1189 324 299 , f ax (44) 1189 328 148 t echnical inqui r ies : german y : (49) 89 95086 0 (munich), united kingdom : (44) 1344 865 900 (bra c knell), france : (33) 1 41 45 77 0 0 (paris), sweden : (46) 8 600 7070 (sto c kholm), finland : (358) 9 4354 2800 (helsinki), i t a l y : (39) 2 6601 1800 (milan), s p ain : (34) 1 807 1441 (mad r id) lucen t t echnologies inc . rese r v es the r ight to ma k e changes to the product(s) or in f o r mation contained herein without notic e . no liability is assumed as a result of their use or application . no r ights under a n y patent accompa n y the sale of a n y such product(s) or in f o r mation . 5ess is a registered tradema r k of lucen t t echnologies inc. co p y r ight ?1998 lucen t t echnologies inc. all rights rese r v e d j a nua r y 1998 ds97-412isdn (replaces ds96-095isdn)

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